Chapter 16
Appendix
Extension Instruction Specification XVI - 59
MACIHU (unsigned halfword data multiply and accumulate instruction: immediate to register)
[Instruction format (macro name)]
MACIHU imm, Dn
[Assembler mnemonic]
udfu31 imm8, Dn : imm8 is 0-extended
udfu31 imm16, Dn
[Operation]
This instruction performs multiply and accumulate operation by means of the multiplier and adder provided in the
extension arithmetic unit.
The instruction multiplies 16-bit data (multiplicand), obtained by 0-extending imm, by the content of Dn
(unsigned 16-bit integer: multiplier), adds this product to the 64-bit accumulative sum whose high-order 32 bits
and low-order 32 bits are stored respectively in the multiply and accumulate registers MCRH and MCRL and
stores high-order 32 bits and low-order 32 bits of the 64-bit result respectively in the multiply and accumulate
registers MCRH and MCRL.
The register outputs a multiply and accumulate overflow detection flag ā1ā to the register MCVF if the
accumulative sum data overflows beyond 64 bits during addition of the product and the accumulative sum.
[Flag changes]
[Note for programming]
An instruction other than extension instructions that requires 1 or more cycles must be inserted between this
instruction and a next extension instruction.
Flag Change Condition
V-
C-
N-
Z-
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