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Renesas HD6417641 - User Manual
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Revision Date: Se
p
. 14
,
2005
32
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family / SH7641 Series
SH7641
HD6417641
Rev.4.00
REJ09B0023-0400
SH7641
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
2
Table of Contents
Main Page
Default Chapter
3
Keep Safety First in Your Circuit Designs
3
Notes Regarding These Materials
3
General Precautions on Handling of Product
4
Configuration of this Manual
6
Table of Contents
13
Section 1 Overview
51
Features
51
Table 1.1 Features
51
Section 1 Overview
52
Section 1 Overview
53
Block Diagram
57
Figure 1.1 Block Diagram
57
Pin Assignments
58
Figure 1.2 Pin Assignments (BGA-256)
58
Pin Functions
59
Table 1.2 Pin Functions
59
Table 1.3 Pin Functions
59
Section 2 CPU
75
Registers
75
Figure 2.1 Register Configuration in each Processing Mode (1)
77
Figure 2.2 Register Configuration in each Processing Mode (2)
78
Table 2.1 Initial Register Values
78
Figure 2.3 General Registers (Not in DSP Mode)
79
General Registers
79
Figure 2.4 General Registers (DSP Mode)
80
Control Registers
81
Figure 2.5 Control Registers (1)
83
Figure 2.5 Control Registers (2)
84
DSP Registers
85
Figure 2.6 System Registers
85
System Registers
85
Table 2.2 Destination Register in DSP Instructions
87
Table 2.3 Source Register in DSP Operations
88
Figure 2.7 DSP Registers
89
Figure 2.8 Connections of DSP Registers and Buses
89
Table 2.4 DSR Register Bits
91
Data Formats
92
Register Data Format (Non-DSP Type)
92
DSP-Type Data Formats
92
Figure 2.9 Longword Operand
92
Figure 2.10 Data Formats
93
Memory Data Formats
94
Features of CPU Core Instructions
94
Figure 2.11 Byte, Word, and Longword Alignment
94
Table 2.5 Word Data Sign Extension
95
Table 2.6 Delayed Branch Instructions
95
Table 2.7 T Bit
96
Table 2.8 Immediate Data Referencing
96
Table 2.9 Absolute Address Referencing
97
Table 2.10 Displacement Referencing
97
Instruction Formats
98
CPU Instruction Addressing Modes
98
Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions
98
DSP Data Addressing
101
Table 2.12 Overview of Data Transfer Instructions
101
Figure 2.12 X and y Data Transfer Addressing
103
Figure 2.13 Single Data Transfer Addressing
104
Figure 2.14 Modulo Addressing
105
CPU Instruction Formats
108
Table 2.13 CPU Instruction Formats
108
DSP Instruction Formats
111
Figure 2.15 DSP Instruction Formats
111
Table 2.14 Double Data Transfer Instruction Formats
112
Table 2.15 Single Data Transfer Instruction Formats
113
Table 2.16 A-Field Parallel Data Transfer Instructions
114
Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (1)
115
Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (2)
116
Instruction Set
117
CPU Instruction Set
117
Table 2.18 CPU Instruction Types
117
Table 2.19 Data Transfer Instructions
121
Table 2.20 Arithmetic Operation Instructions
123
Table 2.21 Logic Operation Instructions
125
Table 2.22 Shift Instructions
126
Table 2.23 Branch Instructions
127
Table 2.24 System Control Instructions
128
DSP Extended-Function Instructions
131
Introduction
131
Added CPU System Control Instructions
132
Table 2.25 Added CPU System Control Instructions
132
Single and Double Data Transfer for DSP Data Instructions
134
Table 2.26 Double Data Transfer Instructions
135
Table 2.27 Single Data Transfer Instructions
136
Table 2.28 Correspondence between DSP Data Transfer Operands and Registers
137
DSP Operation Instruction Set
138
Table 2.29 DSP Operation Instruction Formats
138
Figure 2.16 Sample Parallel Instruction Program
139
Table 2.30 Correspondence between DSP Instruction Operands and Registers
139
Table 2.31 DSP Operation Instructions
140
Table 2.32 DC Bit Update Definitions
146
Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions
147
Table 2.33 Examples of NOPX and NOPY Instruction Codes
148
Section 3 DSP Operation
149
Data Operations of DSP Unit
149
ALU Fixed-Point Operations
149
Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow
149
Table 3.1 Variation of ALU Fixed-Point Operations
150
Table 3.2 Correspondence between Operands and Registers
150
Figure 3.2 Operation Sequence Example
151
Figure 3.3 DC Bit Generation Examples in Carry or Borrow Mode
151
Figure 3.4 DC Bit Generation Examples in Negative Value Mode
152
Figure 3.5 DC Bit Generation Examples in Overflow Mode
152
ALU Integer Operations
154
Figure 3.6 ALU Integer Arithmetic Operation Flow
154
Table 3.3 Variation of ALU Integer Operations
154
ALU Logical Operations
155
Figure 3.7 ALU Logical Operation Flow
156
Table 3.4 Variation of ALU Logical Operations
156
Fixed-Point Multiply Operation
157
Figure 3.8 Fixed-Point Multiply Operation Flow
157
Table 3.5 Variation of Fixed-Point Multiply Operation
158
Table 3.6 Correspondence between Operands and Registers
158
Shift Operations
159
Figure 3.9 Arithmetic Shift Operation Flow
159
Table 3.7 Variation of Shift Operations
159
Figure 3.10 Logical Shift Operation Flow
161
Most Significant Bit Detection Operation
162
Figure 3.11 PDMSB Operation Flow
163
Table 3.8 Operation Definition of PDMSB
164
Rounding Operation
165
Table 3.9 Variation of PDMSB Operation
165
Figure 3.12 Rounding Operation Flow
166
Figure 3.13 Definition of Rounding Operation
166
Table 3.10 Variation of Rounding Operation
166
Overflow Protection
167
Table 3.11 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
167
Table 3.12 Definition of Overflow Protection for Integer Arithmetic Operations
167
Data Transfer Operation
168
Figure 3.14 Data Transfer Operation Flow
169
Figure 3.15 Single Data-Transfer Operation Flow (Word)
170
Figure 3.16 Single Data-Transfer Operation Flow (Longword)
171
Local Data Move Instruction
172
Figure 3.17 Local Data Move Instruction Flow
172
Table 3.13 Variation of Local Data Move Operations
172
Operand Conflict
173
Table 3.14 Correspondence between Operands and Registers
173
DSP Addressing
174
DSP Repeat Control
174
Table 3.15 Address Value to be Stored into SPC (1)
175
Table 3.16 Address Value to be Stored into SPC (2)
176
Figure 3.18 Restriction of Interrupt Acceptance in Repeat Loop
178
Table 3.17 RS and RE Setting Rule
178
DSP Data Addressing
182
Table 3.18 Summary of DSP Data Transfer Instructions
183
Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W
184
Figure 3.20 DSP Addressing Instructions for MOVS
185
Figure 3.21 Modulo Addressing
186
Figure 3.22 Load/Store Control for X and y Data-Transfer Instructions
190
Figure 3.23 Load/Store Control for Single-Data Transfer Instruction
191
Section 4 Clock Pulse Generator (CPG)
193
Features
193
Figure 4.1 Block Diagram of Clock Pulse Generator
194
Input/Output Pins
196
Clock Operating Modes
196
Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator
196
Table 4.2 Clock Operating Modes
196
Table 4.3 Relationship between Clock Mode and Frequency Range
197
Register Descriptions
199
Frequency Control Register (FRQCR)
199
Changing the Frequency
201
Changing the Multiplication Rate
201
Changing the Division Ratio
201
Notes on Board Design
202
Figure 4.2 Note on Using a Crystal Resonator
202
Figure 4.3 Note on Using a PLL Oscillator Circuit
203
Section 5 Watchdog Timer (WDT)
205
Features
205
Register Descriptions
206
Watchdog Timer Counter (WTCNT)
206
Figure 5.1 Block Diagram of the WDT
206
Watchdog Timer Control/Status Register (WTCSR)
207
Notes on Register Access
209
Use of the WDT
209
Canceling Standbys
209
Figure 5.2 Writing to WTCNT and WTCSR
209
Changing the Frequency
210
Using Watchdog Timer Mode
210
Using Interval Timer Mode
211
Precautions to Take When Using the WDT
211
Section 6 Power-Down Modes
213
Features
213
Power-Down Modes
213
Power-On Reset
214
Table 6.1 States of Power-Down Modes
214
Input/Output Pins
215
Table 6.2 Pin Configuration
215
Register Descriptions
216
Standby Control Register (STBCR)
216
Standby Control Register 2 (STBCR2)
217
Standby Control Register 3 (STBCR3)
218
Standby Control Register 4 (STBCR4)
220
Operation
221
Sleep Mode
221
Standby Mode
222
Table 6.3 Register States in Standby Mode
222
Figure 6.1 Canceling Standby Mode with STBCR.STBY
223
Module Standby Function
224
STATUS Pin Change Timings
224
Figure 6.2 STATUS Output at Manual Reset
225
Figure 6.3 STATUS Output When Standby Mode Is Canceled by an Interrupt
225
Figure 6.4 STATUS Output When Software Standby Mode Is Canceled by a Manual Reset
226
Figure 6.5 STATUS Output When Sleep Mode Is Canceled by an Interrupt
226
Figure 6.6 STATUS Output When Sleep Mode Is Canceled by a Manual Reset
227
Section 7 Cache
229
Features
229
Table 7.1 Cache Specifications
229
Table 7.2 Address Space Subdivisions and Cache Operation
229
Cache Structure
230
Figure 7.1 Cache Structure
230
Table 7.3 LRU and Way Replacement
231
Register Descriptions
232
Cache Control Register 1 (CCR1)
232
Cache Control Register 2 (CCR2)
233
Table 7.4 Way to be Replaced When a Cache Miss Occurs in PREF Instruction
235
Table 7.5 Way to be Replaced When a Cache Miss Occurs in Other than PREF Instruction
235
Table 7.6 LRU and Way Replacement (When W2LOCK=1 and W3LOCK=0)
235
Cache Operation
236
Searching Cache
236
Table 7.8 LRU and Way Replacement (When W2LOCK=1 and W3LOCK=1)
236
Figure 7.2 Cache Search Scheme
237
Read Access
238
Prefetch Operation
238
Write Access
238
Write-Back Buffer
239
Coherency of Cache and External Memory
239
Figure 7.3 Write-Back Buffer Configuration
239
Memory-Mapped Cache
240
Address Array
240
Data Array
240
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
241
Usage Examples
242
Section 8 X/Y Memory
243
Features
243
X/Y Memory Access from CPU
244
X/Y Memory Access from DSP
244
Figure 8.1 X/Y Memory Address Mapping
244
X/Y Memory Access from DMAC
245
Usage Note
245
Sleep Mode
245
Address Error
245
Section 9 Exception Handling
247
Register Descriptions
248
TRAPA Exception Register (TRA)
248
Figure 9.1 Register Bit Configuration
248
Exception Event Register (EXPEVT)
249
Interrupt Event Register 2 (INTEVT2)
249
Exception Handling Function
250
Exception Handling Flow
250
Exception Vector Addresses
251
Exception Codes
251
Exception Request and BL Bit (Multiple Exception Prevention)
251
Exception Source Acceptance Timing and Priority
252
Individual Exception Operations
255
Resets
255
General Exceptions
256
Table 9.2 Type of Reset
256
Exception Processing While DSP Extension Function Is Valid
260
Illegal Instruction Exception and Slot Illegal Instruction Exception
260
Exception in Repeat Control Period
260
Table 9.3 Instruction Positions and Restriction Types
260
Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
263
Table 9.5 Exception Acceptance in the Repeat Loop
264
Table 9.6 Instruction Where a Specific Exception Occurs When a Memory Access Exception Occurs in Repeat Control
265
Note on Initializing this LSI
266
Usage Notes
268
Section 10 Interrupt Controller (INTC)
269
Features
269
Figure 10.1 Block Diagram of INTC
270
Input/Output Pins
271
Register Descriptions
271
Table 10.1 Pin Configuration
271
Interrupt Priority Registers B to J (IPRB to IPRJ)
273
Table 10.2 Interrupt Sources and IPRB to IPRJ
274
Interrupt Control Register 0 (ICR0)
275
Interrupt Control Register 1 (ICR1)
276
Interrupt Control Register 3 (ICR3)
277
Interrupt Request Register 0 (IRR0)
278
Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
279
Table 10.3 Correspondence between Interrupt Sources and IMR0 to IMR10
280
Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
281
Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10
282
Interrupt Sources
283
NMI Interrupt
283
H-UDI Interrupt
283
IRQ Interrupts
283
On-Chip Peripheral Module Interrupts
284
Interrupt Exception Handling and Priority
285
Table 10.5 Interrupt Exception Handling Sources and Priority
286
INTC Operation
288
Interrupt Sequence
288
Figure 10.2 Interrupt Operation Flowchart
289
Multiple Interrupts
290
Notes on Use
290
Notes on USB Bus Power Control
290
Timing to Clear an Interrupt Source
290
Section 11 User Break Controller (UBC)
291
Features
291
Figure 11.1 Block Diagram of User Break Controller
292
Register Descriptions
293
Break Address Register a (BARA)
293
Break Address Mask Register a (BAMRA)
294
Break Bus Cycle Register a (BBRA)
294
Break Address Register B (BARB)
296
Table 11.1 Specifying Break Address Register
296
Break Address Mask Register B (BAMRB)
297
Break Data Register B (BDRB)
297
Break Data Mask Register B (BDMRB)
298
Table 11.2 Specifying Break Data Register
298
Break Bus Cycle Register B (BBRB)
299
Break Control Register (BRCR)
301
Execution Times Break Register (BETR)
304
Branch Source Register (BRSR)
304
Branch Destination Register (BRDR)
305
Operation
306
Flow of the User Break Operation
306
Break on Instruction Fetch Cycle
307
Break on Data Access Cycle
308
Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
308
Break on X/Y-Memory Bus Cycle
309
Sequential Break
310
Value of Saved Program Counter
310
PC Trace
311
Usage Examples
312
Usage Notes
316
Section 12 Bus State Controller (BSC)
319
Features
319
Figure 12.1 BSC Functional Block Diagram
321
Input/Output Pins
322
Table 12.1 Pin Configuration
322
Area Overview
323
Area Division
323
Shadow Area
324
Figure 12.2 Address Space
324
Address Map
325
Table 12.2 Address Space Map 1 (CMNCR.MAP = 0)
325
Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)
326
Area 0 Memory Type and Memory Bus Width
327
Register Descriptions
327
Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0
327
Common Control Register (CMNCR)
328
Csn Space Bus Control Register (Csnbcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
331
Csn Space Wait Control Register (Csnwcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
336
SDRAM Control Register (SDCR)
364
Refresh Timer Control/Status Register (RTCSR)
367
Refresh Time Constant Register (RTCOR)
369
Refresh Timer Counter (RTCNT)
369
Reset Wait Counter (RWTCNT)
370
Operating Description
371
Endian/Access Size and Data Alignment
371
Table 12.5 32-Bit External Device Access and Data Alignment
371
Table 12.6 16-Bit External Device Access and Data Alignment
372
Table 12.7 8-Bit External Device Access and Data Alignment
373
Normal Space Interface
374
Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)
374
Figure 12.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 0 (Access Wait = 0, Cycle Wait = 0)
375
Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 1 (Access Wait = 0, Cycle Wait = 0)
376
Figure 12.6 Example of 32-Bit Data-Width SRAM Connection
377
Figure 12.7 Example of 16-Bit Data-Width SRAM Connection
378
Figure 12.8 Example of 8-Bit Data-Width SRAM Connection
378
Access Wait Control
379
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)
379
Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal)
380
Csn Assert Period Expansion
381
Figure 12.11 Csn Assert Period Expansion
381
MPX-I/O Interface
382
Figure 12.12 Access Timing for MPX Space (Address Cycle no Wait, Data Cycle no Wait)
382
Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle no Wait)
383
Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
384
SDRAM Interface
385
Figure 12.15 Example of 32-Bit Data Width SDRAM Connection (RASU and CASU Are Not Used)
386
Figure 12.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU Are Not Used)
387
Figure 12.17 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU Are Used)
388
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-1
390
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-2
391
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-1
392
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-2
393
Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and
393
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1
395
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2
396
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1
397
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-2
398
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-1
399
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-2
400
Table 12.14 Relationship between Access Size and Number of Bursts
401
Figure 12.18 Burst Read Basic Timing (cas Latency 1, Auto Pre-Charge)
402
Figure 12.19 Burst Read Wait Specification Timing (cas Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge)
403
Figure 12.20 Basic Timing for Single Read (cas Latency 1, Auto Pre-Charge)
404
Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge)
406
Figure 12.22 Single Write Basic Timing (Auto-Precharge)
407
Figure 12.23 Burst Read Timing (Bank Active, Different Bank, cas Latency 1)
409
Figure 12.24 Burst Read Timing (Bank Active, same Row Addresses in the same Bank, cas Latency 1)
410
Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the same Bank, cas Latency 1)
411
Figure 12.26 Single Write Timing (Bank Active, Different Bank)
412
Figure 12.27 Single Write Timing (Bank Active, same Row Addresses in the same Bank)
413
Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the same Bank)
414
Figure 12.29 Auto-Refresh Timing
416
Figure 12.30 Self-Refresh Timing
417
Figure 12.31 Low-Frequency Mode Access Timing
419
Figure 12.32 Power-Down Mode Access Timing
420
Table 12.15 Access Address in SDRAM Mode Register Write
421
Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC)
423
Figure 12.34 EMRS Command Issue Timing
424
Table 12.16 Output Addresses When EMRS Command Is Issued
424
Figure 12.35 Deep Power-Down Mode Transition Timing
425
Burst ROM (Clock Asynchronous) Interface
426
Table 12.17 Relationship between Bus Width, Access Size, and Number of Bursts
426
Byte-Selection SRAM Interface
427
Figure 12.36 Burst ROM Access Timing (Clock Asynchronous)
427
Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0)
428
Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1)
429
Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
430
Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM
431
Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM
431
Burst MPX-I/O Interface
432
Figure 12.42 Burst MPX Device Connection Example
432
Figure 12.43 Burst MPX Space Access Timing (Single Read, no Wait, or Software Wait 1)
433
Figure 12.44 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1)
434
Figure 12.45 Burst MPX Space Access Timing (Burst Read, no Wait, or Software Wait 1, CS6BWCR.MPXMD = 0)
435
Burst ROM Interface (Clock Synchronous)
436
Figure 12.46 Burst MPX Space Access Timing (Burst Write, no Wait, CS6BWCR.MPXMD = 0)
436
12.5.11 Wait between Access Cycles
437
Figure 12.47 Burst ROM Access Timing (Clock Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1)
437
Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal Space Interface
439
Table 12.19 Minimum Number of Idle Cycles between Access Cycles During DMAC Dual Address Mode Transfer for the Normal Space Interface
440
Table 12.20 Minimum Number of Idle Cycles During DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK
441
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface
443
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface
446
12.5.12 Bus Arbitration
449
Figure 12.48 Bus Arbitration Timing (Clock Mode 7 or CMNCR.HIZCNT = 1)
450
12.5.13 Others
451
Section 13 Direct Memory Access Controller (DMAC)
455
Features
455
Figure 13.1 Block Diagram of the DMAC
456
Input/Output Pins
457
Table 13.1 Pin Configuration
457
Register Descriptions
458
DMA Source Address Registers (SAR)
459
DMA Destination Address Registers (DAR)
459
DMA Transfer Count Registers (DMATCR)
459
DMA Channel Control Registers (CHCR)
460
DMA Operation Register (DMAOR)
466
Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits
470
DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)
471
Table 13.3 Transfer Request Module/Register ID
473
Operation
474
DMA Transfer Flow
474
Figure 13.2 DMA Transfer Flowchart
475
DMA Transfer Requests
476
Table 13.4 Selecting External Request Modes with the RS Bits
476
Table 13.5 Selecting External Request Detection with Dl, DS Bits
477
Table 13.6 Selecting External Request Detection with DO Bit
477
Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits
478
Channel Priority
479
Figure 13.3 Round-Robin Mode
480
Figure 13.4 Changes in Channel Priority in Round-Robin Mode
481
DMA Transfer Types
482
Table 13.8 Supported DMA Transfers
482
Figure 13.5 Data Flow of Dual Address Mode
483
Figure 13.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
484
Figure 13.7 Data Flow in Single Address Mode
485
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode
486
Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)
487
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection)
488
Figure 13.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ Low Level Detection)
488
Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category
489
Number of Bus Cycle States and DREQ Pin Sampling Timing
490
Figure 13.12 Bus State When Multiple Channels Are Operating
490
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
491
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
491
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection
491
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection
492
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection
492
Figure 13.18 BSC Ordinary Memory Access (no Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
493
Completion of DMA Transfer
494
Notes on Usage
495
Notes on DREQ Sampling When DACK Is Divided in External Access
496
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK Is Divided to 4 by Idle Cycles
497
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK Is Divided to 2 by Idle Cycles
497
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK Is Divided to 4 by Idle Cycles
498
Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK Is Divided to 2 by Idle Cycles
499
Section 14 U Memory
501
Features
501
Table 14.1 U Memory Specifications
501
U Memory Access from CPU
502
U Memory Access from DSP
502
U Memory Access from DMAC
502
Figure 14.1 U Memory Address Mapping
502
Usage Note
503
Sleep Mode
503
Address Error
503
Section 15 User Debugging Interface (H-UDI)
505
Features
505
Figure 15.1 Block Diagram of H-UDI
505
Input/Output Pins
506
Table 15.1 Pin Configuration
506
Register Descriptions
507
Bypass Register (SDBPR)
507
Instruction Register (SDIR)
507
Boundary Scan Register (SDBSR)
508
Table 15.2 H-UDI Commands
508
Table 15.3 this LSI Pins and Boundary Scan Register Bits
509
ID Register (SDID)
517
Operation
518
TAP Controller
518
Figure 15.2 TAP Controller State Transitions
518
Reset Configuration
519
TDO Output Timing
519
Table 15.4 Reset Configuration
519
H-UDI Reset
520
H-UDI Interrupt
520
Figure 15.3 H-UDI Data Transfer Timing
520
Figure 15.4 H-UDI Reset
520
Boundary Scan
521
Supported Instructions
521
Points for Attention
522
Usage Notes
522
Section 16 I C Bus Interface 2 (IIC2)
523
Features
523
C Bus Interface
524
Figure 16.1 Block Diagram of I
524
Input/Output Pins
525
Figure 16.2 External Circuit Connections of I/O Pins
525
I 2 C Bus Interrupt Enable Register (ICIER)
526
I 2 C Bus Mode Register (ICMR)
526
Register Descriptions
526
C Bus Control Register 1 (ICCR1)
526
Table 16.2 Transfer Rate
528
C Bus Control Register 2 (ICCR2)
529
C Bus Mode Register (ICMR)
530
C Bus Interrupt Enable Register (ICIER)
532
C Bus Status Register (ICSR)
534
Slave Address Register (SAR)
536
C Bus Transmit Data Register (ICDRT)
537
C Bus Receive Data Register (ICDRR)
537
C Bus Shift Register (ICDRS)
537
NF2CYC Register (NF2CYC)
537
Operation
538
C Bus Format
538
Figure 16.3 I 2 C Bus Formats
538
Figure 16.4 I 2 C Bus Timing
538
Master Transmit Operation
539
Figure 16.5 Master Transmit Mode Operation Timing (1)
540
Figure 16.6 Master Transmit Mode Operation Timing (2)
540
Master Receive Operation
541
Figure 16.7 Master Receive Mode Operation Timing (1)
542
Slave Transmit Operation
543
Figure 16.8 Master Receive Mode Operation Timing (2)
543
Figure 16.9 Slave Transmit Mode Operation Timing (1)
544
Figure 16.10 Slave Transmit Mode Operation Timing (2)
545
Slave Receive Operation
546
Figure 16.11 Slave Receive Mode Operation Timing (1)
546
Figure 16.12 Slave Receive Mode Operation Timing (2)
547
Clocked Synchronous Serial Format
547
Data Transfer Format
547
Figure 16.13 Clocked Synchronous Serial Transfer Format
547
Figure 16.14 Transmit Mode Operation Timing
548
Figure 16.15 Receive Mode Operation Timing
550
Figure 16.16 Operation Timing for Receiving One Byte
550
Noise Filter
551
Figure 16.17 Block Diagram of Noise Filter
551
Example of Use
552
Figure 16.18 Sample Flowchart for Master Transmit Mode
552
Figure 16.19 Sample Flowchart for Master Receive Mode
553
Figure 16.20 Sample Flowchart for Slave Transmit Mode
554
Figure 16.21 Sample Flowchart for Slave Receive Mode
555
Interrupt Request
556
Table 16.3 Interrupt Requests
556
Bit Synchronous Circuit
557
Figure 16.22 the Timing of the Bit Synchronous Circuit
557
Table 16.4 Time for Monitoring SCL
557
Usage Note
558
Section 17 Compare Match Timer (CMT)
559
Features
559
Figure 17.1 Block Diagram of Compare Match Timer
559
Register Descriptions
560
Compare Match Timer Start Register (CMSTR)
560
Compare Match Timer Control/Status Register (CMCSR)
561
Compare Match Counter (CMCNT )
562
Compare Match Constant Register (CMCOR)
562
Operation
563
Interval Count Operation
563
CMCNT Count Timing
563
Figure 17.2 Counter Operation
563
Figure 17.3 Count Timing
563
Compare Matches
564
Timing of Compare Match Flag Setting
564
DMA Transfer Requests and Interrupt Requests
564
Figure 17.4 Timing of CMF Setting
564
Timing of Compare Match Flag Clearing
565
Section 18 Multi-Function Timer Pulse Unit (MTU)
567
Features
567
Table 18.1 MTU Functions
568
Figure 18.1 Block Diagram of MTU
570
Input/Output Pins
571
Table 18.2 MTU Pin Configuration
571
Register Descriptions
572
Timer Control Register (TCR)
574
Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4)
575
Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2)
575
Table 18.5 TPSC0 to TPSC2 (Channel 0)
576
Table 18.6 TPSC0 to TPSC2 (Channel 1)
576
Table 18.7 TPSC0 to TPSC2 (Channel 2)
577
Table 18.8 TPSC0 to TPSC2 (Channels 3 and 4)
577
Timer Mode Register (TMDR)
578
Table 18.9 MD0 to MD3
579
Timer I/O Control Register (TIOR)
580
Table 18.10 TIORH_0 (Channel 0)
582
Table 18.11 TIORL_0 (Channel 0)
583
Table 18.12 TIOR_1 (Channel 1)
584
Table 18.13 TIOR_2 (Channel 2)
585
Table 18.14 TIORH_3 (Channel 3)
586
Table 18.15 TIORL_3 (Channel 3)
587
Table 18.16 TIORH_4 (Channel 4)
588
Table 18.17 TIORL_4 (Channel 4)
589
Table 18.18 TIORH_0 (Channel 0)
590
Table 18.19 TIORL_0 (Channel 0)
591
Table 18.20 TIOR_1 (Channel 1)
592
Table 18.21 TIOR_2 (Channel 2)
593
Table 18.22 TIORH_3 (Channel 3)
594
Table 18.23 TIORL_3 (Channel 3)
595
Table 18.24 TIORH_4 (Channel 4)
596
Table 18.25 TIORL_4 (Channel 4)
597
Timer Interrupt Enable Register (TIER)
598
Timer Status Register (TSR)
600
Timer Counter (TCNT)
603
Timer General Register (TGR)
603
Timer Start Register (TSTR)
604
Timer Synchro Register (TSYR)
604
Timer Output Master Enable Register (TOER)
606
Timer Output Control Register (TOCR)
607
Table 18.26 Output Level Select Function
607
Figure 18.2 Complementary PWM Mode Output Level Example
608
Table 18.27 Output Level Select Function
608
Timer Gate Control Register (TGCR)
609
Table 18.28 Output Level Select Function
610
Timer Subcounter (TCNTS)
611
Timer Dead Time Data Register (TDDR)
611
Timer Period Data Register (TCDR)
611
Timer Period Buffer Register (TCBR)
611
18.3.17 Bus Master Interface
612
Operation
612
Basic Functions
612
Figure 18.3 Example of Counter Operation Setting Procedure
613
Figure 18.4 Free-Running Counter Operation
614
Figure 18.5 Periodic Counter Operation
614
Figure 18.6 Example of Setting Procedure for Waveform Output by Compare Match
615
Figure 18.7 Example of 0 Output/1 Output Operation
615
Figure 18.8 Example of Toggle Output Operation
616
Figure 18.9 Example of Input Capture Operation Setting Procedure
617
Synchronous Operation
618
Figure 18.10 Example of Input Capture Operation
618
Figure 18.11 Example of Synchronous Operation Setting Procedure
619
Figure 18.12 Example of Synchronous Operation
620
Buffer Operation
621
Figure 18.13 Compare Match Buffer Operation
621
Table 18.29 Register Combinations in Buffer Operation
621
Figure 18.14 Input Capture Buffer Operation
622
Figure 18.15 Example of Buffer Operation Setting Procedure
622
Figure 18.16 Example of Buffer Operation (1)
623
Cascaded Operation
624
Figure 18.17 Example of Buffer Operation (2)
624
Table 18.30 Cascaded Combinations
624
Figure 18.18 Cascaded Operation Setting Procedure
625
Figure 18.19 Example of Cascaded Operation
625
PWM Modes
626
Table 18.31 PWM Output Registers and Output Pins
627
Figure 18.20 Example of PWM Mode Setting Procedure
628
Figure 18.21 Example of PWM Mode Operation (1)
628
Figure 18.22 Example of PWM Mode Operation (2)
629
Figure 18.23 Example of PWM Mode Operation (3)
630
Phase Counting Mode
631
Table 18.32 Phase Counting Mode Clock Input Pins
631
Figure 18.24 Example of Phase Counting Mode Setting Procedure
632
Figure 18.25 Example of Phase Counting Mode 1 Operation
632
Figure 18.26 Example of Phase Counting Mode 2 Operation
633
Table 18.33 Up/Down-Count Conditions in Phase Counting Mode 1
633
Figure 18.27 Example of Phase Counting Mode 3 Operation
634
Table 18.34 Up/Down-Count Conditions in Phase Counting Mode 2
634
Figure 18.28 Example of Phase Counting Mode 4 Operation
635
Table 18.35 Up/Down-Count Conditions in Phase Counting Mode 3
635
Table 18.36 Up/Down-Count Conditions in Phase Counting Mode 4
636
Figure 18.29 Phase Counting Mode Application Example
637
Reset-Synchronized PWM Mode
638
Table 18.37 Output Pins for Reset-Synchronized PWM Mode
638
Table 18.38 Register Settings for Reset-Synchronized PWM Mode
638
Figure 18.30 Procedure for Selecting the Reset-Synchronized PWM Mode
639
Figure 18.31 Reset-Synchronized PWM Mode Operation Example (When the Tocr's OLSN = 1 and OLSP = 1)
640
Complementary PWM Mode
641
Table 18.39 Output Pins for Complementary PWM Mode
641
Table 18.40 Register Settings for Complementary PWM Mode
642
Figure 18.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
643
Figure 18.33 Example of Complementary PWM Mode Setting Procedure
644
Figure 18.34 Complementary PWM Mode Counter Operation
646
Figure 18.35 Example of Complementary PWM Mode Operation
647
Table 18.41 Registers and Counters Requiring Initialization
648
Figure 18.36 Example of PWM Cycle Updating
650
Figure 18.37 Example of Data Update in Complementary PWM Mode
651
Figure 18.38 Example of Initial Output in Complementary PWM Mode (1)
652
Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)
653
Figure 18.40 Example of Complementary PWM Mode Waveform Output (1)
655
Figure 18.41 Example of Complementary PWM Mode Waveform Output (2)
656
Figure 18.42 Example of Complementary PWM Mode Waveform Output (3)
657
Figure 18.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
658
Figure 18.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)
659
Figure 18.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
659
Figure 18.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)
660
Figure 18.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
660
Figure 18.48 Example of Toggle Output Waveform Synchronized with PWM Output
661
Figure 18.49 Counter Clearing Synchronized with Another Channel
662
Figure 18.50 Example of Output Phase Switching by External Input (1)
663
Figure 18.51 Example of Output Phase Switching by External Input (2)
664
Figure 18.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)
664
Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)
665
Interrupts
666
Interrupts and Priority
666
Table 18.42 MTU Interrupts
667
DMA Activation
668
A/D Converter Activation
668
Operation Timing
669
Input/Output Timing
669
Figure 18.54 Count Timing in Internal Clock Operation
669
Figure 18.55 Count Timing in External Clock Operation
669
Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode)
670
Figure 18.57 Output Compare Output Timing (Normal Mode/Pwm Mode)
670
Figure 18.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode)
671
Figure 18.59 Input Capture Input Signal Timing
671
Figure 18.60 Counter Clear Timing (Compare Match)
672
Figure 18.61 Counter Clear Timing (Input Capture)
672
Figure 18.62 Buffer Operation Timing (Compare Match)
673
Figure 18.63 Buffer Operation Timing (Input Capture)
673
Interrupt Signal Timing
674
Figure 18.64 TGI Interrupt Timing (Compare Match)
674
Figure 18.65 TGI Interrupt Timing (Input Capture)
674
Figure 18.66 TCIV Interrupt Setting Timing
675
Figure 18.67 TCIU Interrupt Setting Timing
675
Figure 18.68 Timing for Status Flag Clearing by the CPU
676
Figure 18.69 Timing for Status Flag Clearing by DMA Activation
676
Usage Notes
677
Module Standby Mode Setting
677
Input Clock Restrictions
677
Figure 18.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
677
Caution on Period Setting
678
Conflict between TCNT Write and Clear Operations
678
Figure 18.71 Conflict between TCNT Write and Clear Operations
678
Conflict between TCNT Write and Increment Operations
679
Figure 18.72 Conflict between TCNT Write and Increment Operations
679
Conflict between TGR Write and Compare Match
680
Conflict between Buffer Register Write and Compare Match
680
Figure 18.73 Conflict between TGR Write and Compare Match
680
Channels 3 and
681
Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0)
681
Figure 18.75 Conflict between Buffer Register Write and Compare Match (Channels 3 and 4)
681
Conflict between TGR Read and Input Capture
682
Figure 18.76 Conflict between TGR Read and Input Capture
682
Conflict between TGR Write and Input Capture
683
Figure 18.77 Conflict between TGR Write and Input Capture
683
18.7.10 Conflict between Buffer Register Write and Input Capture
684
18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection
684
Figure 18.78 Conflict between Buffer Register Write and Input Capture
684
Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection
685
18.7.12 Counter Value During Complementary PWM Mode Stop
686
18.7.13 Buffer Operation Setting in Complementary PWM Mode
686
Figure 18.80 Counter Value During Complementary PWM Mode Stop
686
18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
687
Figure 18.81 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode
687
18.7.15 Overflow Flags in Reset Sync PWM Mode
688
18.7.16 Conflict between Overflow/Underflow and Counter Clearing
688
Figure 18.82 Reset Sync PWM Mode Overflow Flag
688
18.7.17 Conflict between TCNT Write and Overflow/Underflow
689
Figure 18.83 Conflict between Overflow and Counter Clearing
689
Figure 18.84 Conflict between TCNT Write and Overflow
689
18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to
690
Reset-Synchronous PWM Mode
690
18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
690
18.7.20 Interrupts in Module Standby Mode
690
Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection
690
MTU Output Pin Initialization
691
Operating Modes
691
Reset Start Operation
691
Operation in Case of Re-Setting Due to Error During Operation, Etc
692
Table 18.43 Mode Transition Combinations
692
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc
693
Figure 18.85 Error Occurrence in Normal Mode, Recovery in Normal Mode
694
Figure 18.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1
695
Figure 18.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2
696
Figure 18.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode
697
Figure 18.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode
698
Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous
699
Figure 18.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode
700
Figure 18.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1
701
Figure 18.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2
702
Figure 18.94 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode
703
Figure 18.95 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode
704
Figure 18.96 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous
705
Figure 18.97 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
706
Figure 18.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1
707
Figure 18.99 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2
708
Figure 18.100 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode
709
Figure 18.101 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode
710
Figure 18.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1
711
Figure 18.103 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2
712
Figure 18.104 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode
713
Figure 18.105 Error Occurrence in Complementary PWM Mode, Recovery in
714
Figure 18.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1
715
Figure 18.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode
716
Figure 18.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode
717
Figure 18.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode
718
Figure 18.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in
719
Figure 18.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in
720
Figure 18.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode
721
Figure 18.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode
722
Port Output Enable (POE)
723
Features
723
Figure 18.114 POE Block Diagram
724
Pin Configuration
725
Register Configuration
725
Table 18.44 Pin Configuration
725
Table 18.45 Pin Combinations
725
Operation
731
Figure 18.115 Falling Edge Detection Operation
731
Figure 18.116 Low-Level Detection Operation
732
Figure 18.117 Output-Level Detection Operation
732
Section 19 Serial Communication Interface with FIFO (SCIF)
735
Overview
735
Features
735
Figure 19.1 Block Diagram of SCIF
737
Pin Configuration
738
Table 19.1 SCIF Pins
738
Register Description
739
Receive Shift Register (SCRSR)
740
Receive FIFO Data Register (SCFRDR)
740
Transmit Shift Register (SCTSR)
740
Transmit FIFO Data Register (SCFTDR)
741
Serial Mode Register (SCSMR)
741
Section 19.3.8, Bit Rate Register (SCBRR)
744
Serial Control Register (SCSCR)
745
Serial Status Register (SCFSR)
749
Bit Rate Register (SCBRR)
757
Table 19.2 SCSMR Settings
757
Table 19.3 Bit Rates and SCBRR Settings in Asynchronous Mode
758
Table 19.4 Bit Rates and SCBRR Settings in Synchronous Mode
761
Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
762
Table 19.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
763
Table 19.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
763
FIFO Control Register (SCFCR)
764
FIFO Data Count Register (SCFDR)
767
Serial Port Register (SCSPTR)
767
Line Status Register (SCLSR)
770
Operation
771
Overview
771
Table 19.8 SCSMR Settings and SCIF Communication Formats
772
Table 19.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection
772
Operation in Asynchronous Mode
773
Figure 19.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)
773
Table 19.10 Serial Communication Formats (Asynchronous Mode)
774
Figure 19.3 Sample Flowchart for SCIF Initialization
776
Figure 19.4 Sample Flowchart for Transmitting Serial Data
777
Figure 19.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)
779
Figure 19.6 Example of Operation Using Modem Control (CTS)
779
Figure 19.7 Sample Flowchart for Receiving Serial Data
780
Figure 19.8 Sample Flowchart for Receiving Serial Data (Cont)
781
Synchronous Operation
783
Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)
783
Figure 19.10 Example of Operation Using Modem Control (RTS)
783
Figure 19.11 Data Format in Synchronous Communication
784
Figure 19.12 Sample Flowchart for SCIF Initialization
785
Figure 19.13 Sample Flowchart for Transmitting Serial Data
786
Figure 19.14 Example of SCIF Transmit Operation
787
Figure 19.15 Sample Flowchart for Receiving Serial Data (1)
788
Figure 19.16 Sample Flowchart for Receiving Serial Data (2)
789
Figure 19.17 Example of SCIF Receive Operation
790
Figure 19.18 Sample Flowchart for Transmitting/Receiving Serial Data
791
SCIF Interrupts and DMAC
792
Usage Notes
793
Table 19.11 SCIF Interrupt Sources
793
Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode
795
Figure 19.20 DMA Transfer Example in the Synchronization Clock
796
Section 20 USB Function Module
797
Features
797
Block Diagram
798
Pin Configuration
798
Figure 20.1 Block Diagram of USB
798
Table 20.1 Pin Configuration and Functions
798
Register Descriptions
799
USB Interrupt Flag Register 0 (USBIFR0)
800
USB Interrupt Flag Register 1 (USBIFR1)
801
USB Interrupt Flag Register 2 (USBIFR2)
802
USB Interrupt Select Register 0 (USBISR0)
803
USB Interrupt Select Register 1 (USBISR1)
804
USB Interrupt Enable Register 0 (USBIER0)
804
USB Interrupt Enable Register 1 (USBIER1)
805
USB Interrupt Enable Register 2 (USBIER2)
805
Usbep0I Data Register (Usbepdr0I)
806
Usbep0O Data Register (Usbepdr0O)
806
Usbep0S Data Register (Usbepdr0S)
807
USBEP1 Data Register (USBEPDR1)
807
USBEP2 Data Register (USBEPDR2)
808
USBEP3 Data Register (USBEPDR3)
808
Usbep0O Receive Data Size Register (Usbepsz0O)
808
USBEP1 Receive Data Size Register (USBEPSZ1)
809
USB Trigger Register (USBTRG)
809
USB Data Status Register (USBDASTS)
810
USBFIFO Clear Register (USBFCLR)
811
USBDMA Transfer Setting Register (USBDMAR)
812
USB Endpoint Stall Register (USBEPSTL)
813
USB Transceiver Control Register (USBXVERCR)
814
USB Bus Power Control Register (USBCTRL)
815
Operation
816
Cable Connection
816
External Circuitry
816
Figure 20.2 Cable Connection Operation
816
Cable Disconnection
817
Figure 20.3 Cable Disconnection Operation
817
Control Transfer
818
Figure 20.4 Transfer Stages in Control Transfer
818
Figure 20.5 Setup Stage Operation
819
Figure 20.6 Data Stage (Control-IN) Operation
820
Figure 20.7 Data Stage (Control-OUT) Operation
821
Figure 20.8 Status Stage (Control-IN) Operation
822
Figure 20.9 Status Stage (Control-OUT) Operation
823
EP1 Bulk-OUT Transfer (Dual Fifos)
824
Figure 20.10 EP1 Bulk-OUT Transfer Operation
825
EP2 Bulk-IN Transfer (Dual Fifos)
826
Figure 20.11 EP2 Bulk-IN Transfer Operation
827
EP3 Interrupt-IN Transfer
828
Figure 20.12 EP3 Interrupt-IN Transfer Operation
828
Processing of USB Standard Commands and Class/Vendor Commands
829
Processing of Commands Transmitted by Control Transfer
829
Table 20.2 Command Decoding on Application Side
829
Stall Operations
830
Forcible Stall by Application
830
Figure 20.13 Forcible Stall by Application
831
Automatic Stall by USB Function Module
832
Figure 20.14 Automatic Stall by USB Function Module
833
DMA Transfer
834
DMA Transfer for Endpoint 1
834
Figure 20.15 EP1 RDFN Operation
834
DMA Transfer for Endpoint 2
835
Figure 20.16 EP2 PKTE Operation
835
Example of USB External Circuitry
836
Figure 20.17 Example of USB Function Module External Circuitry (for On-Chip Transceiver)
837
Figure 20.18 Example of USB Function Module External Circuitry (for External Transceiver)
838
USB Bus Power Control Method
839
USB Bus Power Control Operation
839
Usage Example of USB Bus Power Control Method
840
Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry
840
Figure 20.20 USB Standby Operation Timing
840
Figure 20.21 Sample Flowchart for Initialization of the USB Bus Power Control Method
841
Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby
842
Figure 20.23 Sample Flowchart for AWAKE
843
Notes on Usage
844
20.10.1 Receiving Setup Data
844
20.10.2 Clearing FIFO
844
20.10.3 Overreading or Overwriting Data Register
844
20.10.4 Assigning Interrupt Source for EP0
845
20.10.5 Clearing FIFO When Setting DMA Transfer
845
20.10.6 Manual Reset for DMA Transfer
845
20.10.7 USB Clock
845
20.10.8 Using TR Interrupt
845
Figure 20.24 Timing for Setting the TR Interrupt Flag
846
Section 21 A/D Converter
847
Features
847
Block Diagram
848
Figure 21.1 Block Diagram of A/D Converter
848
Input Pins
849
Table 21.1 A/D Converter Pins
849
Register Configuration
850
Register Descriptions
850
A/D Data Registers a to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)
850
A/D Control/Status Registers (ADCSR0, ADCSR1)
851
Table 21.2 Analog Input Channels and A/D Data Registers
851
A/D0, A/D1 Control Register (ADCR)
854
Operation
855
Single Mode
855
Multi Mode
856
Figure 21.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
856
Figure 21.3 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected)
857
Scan Mode
858
Simultaneous Sampling Operation
859
Figure 21.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
859
A/D Converter Activation by MTU
860
Input Sampling and A/D Conversion Time
860
Figure 21.5 A/D Conversion Timing
861
Table 21.3 A/D Conversion Time (Single Mode)
861
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
861
Interrupt and DMAC Transfer Request
862
Table 21.5 Interrupt and DMAC Transfer Request
862
Definitions of A/D Conversion Accuracy
863
Figure 21.6 Definitions of A/D Conversion Accuracy
864
Usage Notes
865
Setting Analog Input Voltage
865
Processing of Analog Input Pins
865
Permissible Signal Source Impedance
865
Influences on Absolute Precision
866
Stop During A/D Conversion
866
Figure 21.7 Example of Analog Input Protection Circuit
867
Figure 21.8 Analog Input Pin Equivalent Circuit
867
Figure 21.9 Example of Analog Input Circuit
867
Section 22 Pin Function Controller (PFC)
869
Table 22.1 List of Multiplexed Pins
869
Register Descriptions
873
Port a Control Register (PACR)
874
Port B Control Register (PBCR)
876
Port C Control Register (PCCR)
877
Port D Control Register (PDCR)
878
Port E Control Register (PECR)
880
Port E I/O Register (PEIOR)
882
Port E MTU R/W Enable Register (PEMTURWER)
883
Port F Control Register (PFCR)
884
Port G Control Register
886
Port H Control Register (PHCR)
888
Port J Control Register (PJCR)
889
I/O Buffer Internal Block Diagram
891
I/O Buffer with Weak Keeper
891
I/O Buffer with Open Drain Output
891
Figure 22.1 Internal Block Diagram of I/O Buffer with Weak Keeper
891
Notes on Usage
892
Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain
892
Section 23 I/O Ports
893
Port a
893
Register Description
893
Figure 23.1 Port a
893
Port a Data Register (PADR)
894
Port B
895
Register Description
895
Figure 23.2 Port B
895
Table 23.1 Port a Data Register (PADR) Read/Write Operations
895
Port B Data Register (PBDR)
896
Table 23.2 Port B Data Register (PBDR) Read/Write Operations
896
Port C
897
Register Description
897
Figure 23.3 Port C
897
Port C Data Register (PCDR)
898
Port D
899
Figure 23.4 Port D
899
Table 23.3 Port C Data Register (PCDR) Read/Write Operations
899
Port D Data Register (PDDR)
900
Register Description
900
Port E
901
Figure 23.5 Port E
901
Table 23.4 Port D Data Register (PDDR) Read/Write Operations
901
Port E Data Register (PEDR)
902
Register Description
902
Port F
903
Figure 23.6 Port F
903
Table 23.5 Port E Data Register (PEDR) Read/Write Operations
903
Port F Data Register (PFDR)
904
Register Description
904
Table 23.6 Port F Data Register (PFDR) Read/Write Operations (PF15DT to PF8DT)
905
Table 23.7 Port F Data Register (PFDR) Read/Write Operations (PF7DT to PF0DT)
905
Port G
906
Register Description
906
Figure 23.7 Port G
906
Port G Data Register
907
Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT, PG8DT)
908
Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT)
908
Table 23.10 Port G Data Register (PGDR) Read/Write Operations (PG7DT to PG0DT)
908
Port G Internal Block Diagram
909
Figure 23.8 Internal Block Diagram of PG7DT to PG0DT
909
Port H
910
Register Description
910
Figure 23.9 Port H
910
Port H Data Register (PHDR)
911
Port J
912
Register Description
912
Figure 23.10 Port J
912
Table 23.11 Port H Data Register (PHDR) Read/Write Operations
912
Port J Data Register (PJDR)
913
Table 23.12 Port J Data Register (PJDR) Read/Write Operations
913
Section 24 List of Registers
915
Register Addresses
916
(By Functional Module, in Order of the Corresponding Section Numbers)
916
Register Bits
926
Register States in each Operating Mode
946
Section 25 Electrical Characteristics
957
Absolute Maximum Ratings
957
Table 25.1 Absolute Maximum Ratings
957
Figure 25.1 Power-On Sequence
958
Power-On Sequence
958
Table 25.2 Recommended Values for Power-On/Off Sequence
959
DC Characteristics
960
Table 25.3 DC Characteristics (1) [Common Items]
960
Table 25.3 DC Characteristics (4) [USB-Related Pins]
961
Table 25.3 DC Characteristics (2) [Except for I C- and USB-Related Pins]
963
Table 25.3 DC Characteristics
963
Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins]
964
Table 25.4 Permissible Output Currents
964
AC Characteristics
965
Table 25.5 Maximum Operating Frequency
965
Clock Timing
966
Table 25.6 Clock Timing
966
Figure 25.2 EXTAL Clock Input Timing
967
Figure 25.3 CKIO Clock Input Timing
967
Figure 25.4 CKIO and CKIO2 Clock Input Timing
967
Figure 25.5 Oscillation Settling Timing (Power-On)
968
Figure 25.6 Phase Difference between CKIO and CKIO2
968
Figure 25.7 Oscillation Settling Timing (Standby Mode Canceled by Reset)
968
Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ)
969
Control Signal Timing
970
Table 25.7 Control Signal Timing
970
Figure 25.10 Interrupt Input Timing
971
Figure 25.9 Reset Input Timing
971
Figure 25.11 Bus Release Timing
972
Figure 25.12 Pin Driving Timing in Standby Mode
972
AC Bus Timing
973
Table 25.8 Bus Timing
973
Basic Timing
975
Figure 25.13 Basic Bus Timing for Normal Space (no Wait)
975
Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait)
976
Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/Waitsel = 0)
977
Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/Waitsel = 1)
978
Figure 25.17 Basic Bus Timing for Normal Space (One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), no Idle Cycle)
979
Figure 25.18 MPX-IO Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
980
Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait)
981
Bus Cycle of Byte-Selection SRAM
982
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
982
Figure 25.21 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control))
983
Burst ROM Read Cycle
984
Figure 25.22 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)
984
Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, cas Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
985
Synchronous DRAM Timing
985
Figure 25.24 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, cas Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)
986
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, cas Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
987
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, cas Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
988
Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle)
989
Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)
990
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)
991
Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)
992
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, cas Latency 2, WTRCD = 0 Cycle)
993
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: READ Command, same Row Address, cas Latency 2, WTRCD = 0 Cycle)
994
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, cas Latency 2, WTRCD = 0 Cycle)
995
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle)
996
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle)
997
Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle)
998
Figure 25.37 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles)
999
Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle)
1000
Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)
1001
Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode (Auto-Precharge, TRWL = 2 Cycles)
1002
Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles)
1003
Figure 25.42 SCK Input Clock Timing
1004
Peripheral Module Signal Timing
1004
Table 25.9 Peripheral Module Signal Timing
1004
Figure 25.43 SCIF Input/Output Timing in Synchronous Mode
1005
Figure 25.44 I/O Port Timing
1005
Figure 25.45 DREQ Input Timing
1005
Figure 25.46 DACK, TEND Output Timing
1005
Figure 25.47 MTU Input/Output Timing
1006
Figure 25.48 MTU Clock Input Timing
1006
Multi Function Timer Pulse Unit Timing
1006
Table 25.10 Multi Function Timer Pulse Unit Timing
1006
25.3.10 POE Module Signal Timing
1007
Figure 25.49 POE Input/Output Timing
1007
Table 25.11 Output Enable (POE) Timing
1007
C Module Signal Timing
1008
Table 25.12 I 2 C Bus Interface Timing
1008
Figure 25.50 I C Bus Interface Input/Output Timing
1009
25.3.12 H-UDI Related Pin Timing
1010
Figure 25.51 TCK Input Timing
1010
Table 25.13 H-UDI Related Pin Timing
1010
Figure 25.52 TRST Input Timing (Reset-Hold State)
1011
Figure 25.53 H-UDI Data Transfer Timing
1011
Figure 25.54 Boundary-Scan Input/Output Timing
1011
25.3.13 USB Module Signal Timing
1012
Figure 25.55 USB Clock Timing
1012
Table 25.14 USB Module Clock Timing
1012
Table 25.15 USB Transceiver Timing
1013
USB Transceiver Timing
1013
25.3.15 AC Characteristics Measurement Conditions
1014
Figure 25.56 Output Load Circuit
1014
A/D Converter Characteristics
1015
Table 25.16 A/D Converter Characteristics
1015
A.1 When Other Function Is Selected
1017
Appendix
1017
Pin States
1017
When Other Function Is Selected
1017
When I/O Port Is Selected
1021
Product Lineup
1022
Package Dimensions
1023
Figure C.1 Package Dimensions
1023
Main Revisions and Additions in this Edition
1025
Index
1027
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Renesas HD6417641 Specifications
General
Brand
Renesas
Model
HD6417641
Category
Computer Hardware
Language
English
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