Renesas HD6417641 - Figure 12.32 Power-Down Mode Access Timing

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 370 of 982
REJ09B0023-0400
TnopPower-down
Tr Tc1
Td1 Tde Tap
Power-down
CKIO
CKE
A25 to A0
CSn
RD/WR
RASL, RASU
DQMxx
D31 to D0
BS
DACKn*
2
A12/A11*
1
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.32 Power-Down Mode Access Timing
The conditions to shift to the power-down mode are as follows.
• Write or read access (including instruction fetch) occurs to the memory other than the
SDRAM, which is to be set to the power-down mode.
• Read or write access occurs to the control register with the address H'Axxx xxxx or to the
peripheral I/O register.