Renesas HD6417641 - Section 7 Cache; Features; Table 7.1 Cache Specifications; Table 7.2 Address Space Subdivisions and Cache Operation

Section 7 Cache
Rev. 4.00 Sep. 14, 2005 Page 179 of 982
REJ09B0023-0400
Section 7 Cache
7.1 Features
The cache specifications are listed in table 7.1.
Table 7.1 Cache Specifications
Parameter Specification
Capacity 16 kbytes
Structure Instructions/data mixed, 4-way set associative
Locking Way 2 and way 3 are lockable
Line size 16 bytes
Number of entries 256 entries/way
Write system P0, P1, P3: Write-back/write-through selectable
Replacement method Least-recently-used (LRU) algorithm
In this LSI, the address space is partitioned into five subdivisions, and the cache access method is
determined by the address. Table 7.2 shows the kind of cache access available in each address
space subdivision.
Table 7.2 Address Space Subdivisions and Cache Operation
Address Bits
A31 to 29
Address Space
Subdivision Cache Operation
0xx P0 Write-back/write-through selectable
100 P1 Write-back/write-through selectable
101 P2 Non-cacheable
110 P3 Write-back/write-through selectable
111 P4 I/O area, non-cacheable
Note that area P4 is an I/O area, to which the addresses of on-chip registers, etc., are allocated.
To ensure data consistency, the cache stores 32-bit addresses with the upper 3 bits masked to 0.