Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 421 of 982
REJ09B0023-0400
13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)
DMARS is a 16-bit read/write register that specifies the DMA transfer sources from peripheral
modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for
channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, MTU0,
MTU1, MTU2, MTU3, MTU4, MTU, USB, A/D converter 1, and CMT1.
This register is initialized to H'0000 by power-on manual reset. The previous value is held in
standby mode or module standby mode.
• DMARS0
Bit Bit Name
Initial
Value R/W Description
15
14
13
12
11
10
C1MID5
C1MID4
C1MID3
C1MID2
C1MID1
C1MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request module ID5 for DMA channel 1 (MID).
See table 13.3.
9
8
C1RID1
C1RID0
0
0
R/W
R/W
Transfer request register ID for DMA channel 1 (RID).
See table 13.3.
7
6
5
4
3
2
C0MID5
C0MID4
C0MID3
C0MID2
C0MID1
C0MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request module ID for DMA channel 0 (MID).
See table 13.3
1
0
C0RID1
C0RID0
0
0
R/W
R/W
Transfer request register ID for DMA channel 0 (RID).
See table 13.3.
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