Renesas HD6417641 - Operand Conflict; Table 3.14 Correspondence between Operands and Registers

Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 123 of 982
REJ09B0023-0400
3.1.11 Operand Conflict
When an identical destination operand is specified with multiple parallel instructions, data conflict
occurs. Table 3.14 shows the correspondence between each operand and registers.
Table 3.14 Correspondence between Operands and Registers
X-Memory
Load
Y-Memory
Load
6-Instruction
ALU
3-Instruction
Multiply
3-Instruction
ALU
Ax Ix Dx Ay Iy Dy Sx Sy Du Se Sf Dg Sx Sy Dz
A0 *
1
*
2
*
2
*
1
*
1
A1 *
1
*
2
*
1
*
1
*
2
*
1
*
1
M0 *
1
*
1
*
1
*
1
M1 *
1
*
1
*
1
*
1
X0 *
2
*
1
*
2
*
1
*
1
*
1
*
2
X1 *
2
*
1
*
1
*
1
*
2
Y0 *
2
*
1
*
2
*
1
*
1
*
1
*
2
DSP
Registers
Y1
*
2
*
1
*
1
*
1
*
2
Notes: 1. Registers available for operands
2. Registers available for operands (when there is operand conflict)
There are three cases of operand conflict problems.
1. When ALU and multiply instructions specify the same destination operand (Du and Dg)
2. When X-memory load and ALU instructions specify the same destination operand (Dx, Du,
and Dz)
3. When Y-memory load and ALU instructions specify the same destination operand (Dy, Du,
and Dz)
In these cases above, the result is not guaranteed.