Renesas HD6417641 - Section 23 I;O Ports; Port a; Register Description; Figure 23.1 Port a

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 843 of 982
REJ09B0023-0400
Section 23 I/O Ports
This LSI has nine 16-bit ports (ports A to J). All port pins are multiplexed with other pin functions
(the pin function controller (PFC) handles the selection of pin functions). Each port has a data
register which stores data for the pins.
23.1 Port A
Port A is a 15-bit input/output port with the pin configuration shown in figure 23.1. Each pin is
controlled by the port A control register (PACR) in the PFC.
PTA14 (input/output)/A25 (output)
Port A
PTA13 (input/output)/A24 (output)
PTA12 (input/output)/A23 (output)
PTA11 (input/output)/A22 (output)
PTA10 (input/output)/A21 (output)
PTA9 (input/output)/A20 (output)
PTA8 (input/output)/A19 (output)
PTA7 (input/output)/RASU (output)
PTA6 (input/output)/RASL (output)
PTA5 (input/output)/CASU (output)
PTA4 (input/output)/CASL (output)
PTA3 (input/output)/CS3 (output)
PTA2 (input/output)/CS2 (output)
PTA1 (input/output)/CKE (output)
PTA0 (input/output)/A0 (output)
Figure 23.1 Port A
23.1.1 Register Description
Port A has the following register.
• Port A data register (PADR)