Renesas HD6417641 - Figure 2.14 Modulo Addressing

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 55 of 982
REJ09B0023-0400
MOV.L ModAddr,Rn; Rn=ModEnd, ModStart
LDC Rn,MOD; ME=ModEnd, MS=ModStart
ModAddr: .DATA.W mEnd; ModEnd
.DATA.W mStart; ModStart
ModStart: .DATA
:
ModEnd: .DATA
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1.
When the X/Y data transfer instruction set in DMX/DMY is executed, the address register
contents before update are compared with ME*
1
. If they match, modulo start address MS is stored
in the address register as the updated value*
2
. If non-update address register addressing is
specified for the X/Y data transfer instruction, the address pointer will not return to modulo start
address MS even though the address register contents match ME.
Notes: 1. Bits 1 to 15 of the address register are used for comparison. Though ME retains its
previous value for bit 0, 0 must always be written to bit 0.
2. The MS value is stored in bits 1 to 15 of the address register. Though MS retains its
previous value for bit 0, 0 must always be written to bit 0.
The maximum modulo size is 64-kbytes. This is sufficient to access the X and Y data memory. A
block diagram of modulo addressing is shown in figure 2.14.
ALU
AU
R8[Ix]
R9[Iy]
R6[Ay]
R7[Ay]
+2
+0
31 0
R4[Ax]
R5[Ax]
31 16 15 0
15 1
ABx
XAB
+2
+0
31 0
31 16 15 0
15 1
ABy
YAB
DMX DMY
CONT
MS
CMP
ME
15 1
15 1
Instruction (MOVX/MOVY)
Figure 2.14 Modulo Addressing