Renesas HD6417641 - Figure 18.1 Block Diagram of MTU

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 520 of 982
REJ09B0023-0400
Internal data bus
A/D converter conversion
start signal
TCNT
TGRA TGRB
TGRC TGRD
TCR
TIORH
TIER
TMDR
TIORL
TSR
Channel 3
TCNT
TGRA TGRB
TGRC TGRD
TMDR
TIORL
TSR
TCR
TIORH
TIER
Channel 4
TCNTS
TCDR
TCBR
TDDR
TOER
TOCR TGCR
BUS I/F
Common
TCNT
TGRA TGRB
TMDR
TSR
TCR
TIOR
TIER
TSYR
TSTR
Channel 2
TCNT
TGRA TGRB
TMDR
TSR
TCR
TIOR
TIER
Channel 1
TCNT
TGRA TGRB
TGRC TGRD
TMDR
TIORL
TSR
TCR
TIORH
TIER
Channel 0
Control logic
Module data bus
Control logic for channels 0 to 2 Control logic for channels 3 and 4
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TIER:
TSR:
TCNT:
TGR (A, B, C, D):
Timer interrupt enable register
Timer status register
Timer counter
Timer general registers (A, B, C, D)
Interrupt request signals
Channel 3:
Channel 4:
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4C
TCI4D
TGI4V
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
Input/output pins
Channel 0:
Channel 1:
Channel 2:
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
Internal clock
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
Input/output pins
Channel 3:
Channel 4:
DMA transfer request signal
Channel 0: TGI0A
Channel 1: TGI1A
Channel 2: TGI2A
Channel 0: TGI3A
Channel 1: TGI4A
DMA transfer request signal
TCLKA
TCLKB
TCLKC
TCLKD
External clock
Divider
Figure 18.1 Block Diagram of MTU