Renesas HD6417641 - Table 18.19 TIORL_0 (Channel 0)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 541 of 982
REJ09B0023-0400
Table 18.19 TIORL_0 (Channel 0)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function TIOC0C Pin Function
0 0 0 0 Output hold*
1
1
Output
compare
register*
2
Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output hold*
1
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Input capture at rising edge
1 Input capture at falling edge
1 X Input capture at both edges
1 X X
Input capture
register*
2
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X: Don't care
Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset
and entering standby mode.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.