Renesas HD6417641 - Figure 7.2 Cache Search Scheme

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Section 7 Cache

Rev. 4.00 Sep. 14, 2005 Page 187 of 982

REJ09B0023-0400

255

V U Tag address

LW0 LW1 LW2 LW3

Address array

(ways 0 to 3)

Data array

(ways 0 to 3)

11 4 3 2 1 0

Address

CMP0 CMP1 CMP2 CMP3

Physical address

[Legend]

CMP0: Comparison circuit for way 0

CMP1: Comparison circuit for way 1

CMP2: Comparison circuit for way 2

CMP3: Comparison circuit for way 3

Hit signal (1)

Entry selection Longword (LW) selection

MMU

Figure 7.2 Cache Search Scheme

Main Page

Default Chapter3
- Keep Safety First in Your Circuit Designs3
- Notes Regarding These Materials3
- General Precautions on Handling of Product4
- Configuration of this Manual6
- Table of Contents13
Section 1 Overview51
- Features51
- Block Diagram57
- Figure 1.1 Block Diagram57
- Pin Assignments58
- Figure 1.2 Pin Assignments (BGA-256)58
- Pin Functions59
- Table 1.2 Pin Functions59
- Table 1.3 Pin Functions59
Section 2 CPU75
- Registers75
- Data Formats92
- Features of CPU Core Instructions94
- Figure 2.11 Byte, Word, and Longword Alignment94
- Table 2.5 Word Data Sign Extension95
- Table 2.6 Delayed Branch Instructions95
- Table 2.7 T Bit96
- Table 2.8 Immediate Data Referencing96
- Table 2.9 Absolute Address Referencing97
- Table 2.10 Displacement Referencing97
- Instruction Formats98
- Instruction Set117
- DSP Extended-Function Instructions131
Section 3 DSP Operation149
- Data Operations of DSP Unit149
- DSP Addressing174
Section 4 Clock Pulse Generator (CPG)193
- Features193
- Figure 4.1 Block Diagram of Clock Pulse Generator194
- Input/Output Pins196
- Clock Operating Modes196
- Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator196
- Table 4.2 Clock Operating Modes196
- Table 4.3 Relationship between Clock Mode and Frequency Range197
- Register Descriptions199
  - Frequency Control Register (FRQCR)199
- Changing the Frequency201
  - Changing the Multiplication Rate201
  - Changing the Division Ratio201
- Notes on Board Design202
- Figure 4.2 Note on Using a Crystal Resonator202
- Figure 4.3 Note on Using a PLL Oscillator Circuit203
Section 5 Watchdog Timer (WDT)205
- Features205
- Register Descriptions206
- Use of the WDT209
- Precautions to Take When Using the WDT211
Section 6 Power-Down Modes213
- Features213
- Register Descriptions216
- Operation221
Section 7 Cache229
- Features229
- Register Descriptions232
- Cache Operation236
- Memory-Mapped Cache240
Section 8 X/Y Memory243
- Features243
- X/Y Memory Access from CPU244
- X/Y Memory Access from DSP244
- Figure 8.1 X/Y Memory Address Mapping244
- X/Y Memory Access from DMAC245
- Usage Note245
- Sleep Mode245
- Address Error245
Section 9 Exception Handling247
- Register Descriptions248
- Exception Handling Function250
- Individual Exception Operations255
- Exception Processing While DSP Extension Function Is Valid260
- Note on Initializing this LSI266
- Usage Notes268
Section 10 Interrupt Controller (INTC)269
- Features269
- Figure 10.1 Block Diagram of INTC270
- Input/Output Pins271
- Register Descriptions271
- Interrupt Sources283
- INTC Operation288
- Notes on Use290
  - Notes on USB Bus Power Control290
  - Timing to Clear an Interrupt Source290
Section 11 User Break Controller (UBC)291
- Features291
- Figure 11.1 Block Diagram of User Break Controller292
- Register Descriptions293
- Operation306
- Usage Notes316
Section 12 Bus State Controller (BSC)319
- Features319
- Figure 12.1 BSC Functional Block Diagram321
- Input/Output Pins322
- Table 12.1 Pin Configuration322
- Area Overview323
- Register Descriptions327
- Operating Description371
Section 13 Direct Memory Access Controller (DMAC)455
- Features455
- Figure 13.1 Block Diagram of the DMAC456
- Input/Output Pins457
- Table 13.1 Pin Configuration457
- Register Descriptions458
- Operation474
Section 14 U Memory501
- Features501
- Table 14.1 U Memory Specifications501
- U Memory Access from CPU502
- U Memory Access from DSP502
- U Memory Access from DMAC502
- Figure 14.1 U Memory Address Mapping502
- Usage Note503
- Sleep Mode503
- Address Error503
Section 15 User Debugging Interface (H-UDI)505
- Features505
- Figure 15.1 Block Diagram of H-UDI505
- Input/Output Pins506
- Table 15.1 Pin Configuration506
- Register Descriptions507
- Operation518
- Boundary Scan521
  - Supported Instructions521
  - Points for Attention522
- Usage Notes522
Section 16 I C Bus Interface 2 (IIC2)523
- Features523
- C Bus Interface524
- Figure 16.1 Block Diagram of I524
- Input/Output Pins525
- Register Descriptions526
- Operation538
- Interrupt Request556
- Table 16.3 Interrupt Requests556
- Bit Synchronous Circuit557
- Figure 16.22 the Timing of the Bit Synchronous Circuit557
- Table 16.4 Time for Monitoring SCL557
- Usage Note558
Section 17 Compare Match Timer (CMT)559
- Features559
- Figure 17.1 Block Diagram of Compare Match Timer559
- Register Descriptions560
- Operation563
- Compare Matches564
Section 18 Multi-Function Timer Pulse Unit (MTU)567
- Features567
- Table 18.1 MTU Functions568
- Figure 18.1 Block Diagram of MTU570
- Input/Output Pins571
- Table 18.2 MTU Pin Configuration571
- Register Descriptions572
- Operation612
- Interrupts666
- Operation Timing669
- Usage Notes677
- MTU Output Pin Initialization691
- Port Output Enable (POE)723
Section 19 Serial Communication Interface with FIFO (SCIF)735
- Overview735
  - Features735
  - Figure 19.1 Block Diagram of SCIF737
- Pin Configuration738
- Table 19.1 SCIF Pins738
- Register Description739
- Operation771
- SCIF Interrupts and DMAC792
- Usage Notes793
- Table 19.11 SCIF Interrupt Sources793
- Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode795
- Figure 19.20 DMA Transfer Example in the Synchronization Clock796
Section 20 USB Function Module797
- Features797
  - Block Diagram798
- Pin Configuration798
- Figure 20.1 Block Diagram of USB798
- Table 20.1 Pin Configuration and Functions798
- Register Descriptions799
- Operation816
- Processing of USB Standard Commands and Class/Vendor Commands829
  - Processing of Commands Transmitted by Control Transfer829
  - Table 20.2 Command Decoding on Application Side829
- Stall Operations830
- DMA Transfer834
- Example of USB External Circuitry836
- Figure 20.17 Example of USB Function Module External Circuitry (for On-Chip Transceiver)837
- Figure 20.18 Example of USB Function Module External Circuitry (for External Transceiver)838
- USB Bus Power Control Method839
- Notes on Usage844
Section 21 A/D Converter847
- Features847
- Register Descriptions850
- Operation855
- Interrupt and DMAC Transfer Request862
- Table 21.5 Interrupt and DMAC Transfer Request862
- Definitions of A/D Conversion Accuracy863
- Figure 21.6 Definitions of A/D Conversion Accuracy864
- Usage Notes865
Section 22 Pin Function Controller (PFC)869
- Table 22.1 List of Multiplexed Pins869
- Register Descriptions873
- I/O Buffer Internal Block Diagram891
- Notes on Usage892
- Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain892
Section 23 I/O Ports893
- Port a893
- Port B895
- Port C897
- Port D899
- Port E901
- Port F903
- Port G906
- Port H910
- Port J912
Section 24 List of Registers915
- Register Addresses916
  - (By Functional Module, in Order of the Corresponding Section Numbers)916
- Register Bits926
- Register States in each Operating Mode946
Section 25 Electrical Characteristics957
- Absolute Maximum Ratings957
- DC Characteristics960
- Table 25.3 DC Characteristics (1) [Common Items]960
- Table 25.3 DC Characteristics (4) [USB-Related Pins]961
- Table 25.3 DC Characteristics (2) [Except for I C- and USB-Related Pins]963
- Table 25.3 DC Characteristics963
- Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins]964
- Table 25.4 Permissible Output Currents964
- AC Characteristics965
- A/D Converter Characteristics1015
- Table 25.16 A/D Converter Characteristics1015
- A.1 When Other Function Is Selected1017
Appendix1017
- Pin States1017
  - When Other Function Is Selected1017
  - When I/O Port Is Selected1021
- Product Lineup1022
- Package Dimensions1023
- Figure C.1 Package Dimensions1023
Main Revisions and Additions in this Edition1025
Index1027

Renesas HD6417641 - Figure 7.2 Cache Search Scheme

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