Renesas HD6417641 - C Module Signal Timing; Table 25.12 I 2 C Bus Interface Timing

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 958 of 982
REJ09B0023-0400
25.3.11 I
2
C Module Signal Timing
Table 25.12 I
2
C Bus Interface Timing
Normal Conditions: V
CC
= 1.8 V ± 5%, AV
CC
= V
CC
Q = 3.0 V to 3.6 V, V
SS
= AV
SS
= V
SS
Q = 0 V,
Ta = −40°C to +85°C
Specifications
Item Symbol Test Conditions Min. Typ. Max. Unit Figure(s)
SCL input cycle time t
SCL
12 t
Pcyc
+ 600 — — ns 25.50
SCL input high pulse width t
SCLH
3 t
Pcyc
+ 300 — — ns
SCL input low pulse width t
SCLL
5 t
Pcyc
+ 300 — — ns
SCL, SDA input rising time t
SR
— — 300 ns
SCL, SDA input falling time t
SF
— — 300 ns
SCL, SDA input spike pulse
removal time*
2
t
SP
— — 1.2 t
Pcyc
*
1
SDA input bus free time t
BUF
5 t
Pcyc
— — t
Pcyc
Start condition input hold time t
STAH
3 t
Pcyc
— — t
Pcyc
Retransmit start condition input
setup time
t
STAS
3 t
Pcyc
— — t
Pcyc
Stop condition input setup time t
STOS
3 t
Pcyc
— — t
Pcyc
Data input setup time t
SDAS
1 t
Pcyc
+ 20 — — ns
Data input hold time t
SDAH
0 — — ns
SCL, SDA capacitive load Cb 0 — 400 pF
SCL, SDA output falling time t
SF
V
CC
Q = 3.0 to 3.6 V — — 250*
3
ns
Note: 1. Pcyc indicates peripheral clock cycle.
2. Depends on the value of the register NF2CYC.
3. Indicates the I/O buffer characteristic.