Renesas HD6417641 - Timer Status Register (TSR)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 550 of 982
REJ09B0023-0400
18.3.5 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU has five TSR registers, one for each channel.
Bit Bit Name
Initial
value R/W Description
7 TCFD 1 R Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 3, and 4.
In channel 0, bit 7 is reserved. It is always read as 1,
and should only be written with 1.
0: TCNT counts down
1: TCNT counts up
6  1 R Reserved
This bit is always read as 1. The write value should
always be 1.
5 TCFU 0 R/(W) Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0, and should only be written with 0.
[Setting condition]
• When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1