Renesas HD6417641 - Port G Internal Block Diagram; Figure 23.8 Internal Block Diagram of PG7 DT to PG0 DT

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 859 of 982
REJ09B0023-0400
23.7.3 Port G Internal Block Diagram
Pins PTG7 to PTG0 are multiplexed with the A/D converter. (See section 22, Pin Function
Controller (PFC).) The statuses of these pins are read only when the PGDR is read, but are always
input to the A/D converter.
Figure 23.8 shows the internal block diagram of PG7DT to PG0DT.
Enabled only when the port is read.
Port data register
Port
A/D
Figure 23.8 Internal Block Diagram of PG7DT to PG0DT