Renesas HD6417641 - Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4); Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 525 of 982
REJ09B0023-0400
Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0 Description
0, 3, 4 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input
capture*
2
1 0 TCNT cleared by TGRD compare match/input
capture*
2
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2)
Channel
Bit 7
Reserved*
2
Bit 6
CCLR1
Bit 5
CCLR0 Description
1, 2 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. This bit is always read as 0 and cannot be
modified.