Renesas HD6417641 - Figure 3.23 Load;Store Control for Single-Data Transfer Instruction

Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 141 of 982
REJ09B0023-0400
Single-Data Transfer Instructions (MOVS.W and MOVS.L): This LSI has single load/store
instructions for the DSP registers. It is similar to a load/store instruction for a system register. It
transfers data between memory and DSP data registers using LAB and LDB buses. There may be
access conflict between data access and instruction fetch.
The single-data transfer instruction has word and longword access modes. Figure 3.23 shows a
block diagram of single-data transfer. The existing CPU core's hardware resource is used for
control of the memory address buffer (MAB) and memory selection.
31 0
R2 [As]
R3 [As]
R4 [As]
R5 [As]
LAB
31
0
MAB
Input/output control for
DSP data registers
Memory
32-bit
LDB
32-bit
Instruction code for single data transfer
operation
Control
in CPU
As Ms WL LS Ds
Control
Figure 3.23 Load/Store Control for Single-Data Transfer Instruction