Renesas HD6417641 - Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode (Auto-Precharge, TRWL = 2 Cycles)

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 952 of 982
REJ09B0023-0400
Tr Tc Tnop Trw1 TapTapTdeTd1TcTr
t
AD3
t
AD3
CKIO
A25 to A0
CSn
RD/WR
A12/A11*
1
D31 to D0
RASU/L
CASU/L
BS
CKE
DQMxx
DACKn,
TENDn*
2
t
AD3
t
AD3
t
AD3
t
AD3
Row
address
Column
address
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
CSD2
t
RWD2
t
RWD2
t
RWD2
t
CASD2
t
CASD2
t
CASD2
t
CASD2
t
CASD2
t
RASD2
t
RASD2
t
RASD2
t
RASD2
t
BSD
t
BSD
t
BSD
t
BSD
t
DQMD2
t
DQMD2
t
DQMD2
t
DQMD2
t
RDS4
t
RDH4
t
WDD3
t
WDH3
t
CSD2
t
CSD2
t
CSD2
t
DACD
t
DACD
t
DACD
t
DACD
WriteA
Command
ReadA
Command
Row
address
Column
address
(High) (High)
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn and
TENDn when active low is selected.
Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode
(Auto-Precharge, TRWL = 2 Cycles)