Renesas HD6417641 - Timer Control Register (TCR)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 524 of 982
REJ09B0023-0400
18.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Bit Bit Name
Initial
value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 18.3 and 18.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = φ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is φ/4 or slower. When φ/1,
or the overflow/underflow of another channel is selected
for the input clock, although values can be written,
counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
[Legend]
X: Don't care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 18.5 to 18.8 for details.