Renesas HD6417641 - Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 396 of 982
REJ09B0023-0400
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Address Mode for the SDRAM Interface
(1) Transfer from the external device with DACK to the SDRAM interface
BSC Register Setting*
2
CMNCR.DMAIW
Setting
CS3WCR.WTRP
Setting
CS3WCR.TRWL
Setting
Minimum Number of
Idle Cycles
0 0 0 3
0 0 1 3
0 0 2 3
0 0 3 3
0 1 0 3
0 1 1 3
0 1 2 3
0 1 3 4
0 2 0 3
0 2 1 3
0 2 2 4
0 2 3 5
0 3 0 3
0 3 1 4
0 3 2 5
0 3 3 6
1 0 0 3
1 0 1 3
1 0 2 3
1 0 3 3
1 1 0 3
1 1 1 3
1 1 2 3
1 1 3 4
1 2 0 3
1 2 1 3
1 2 2 4
1 2 3 5
1 3 0 3
1 3 1 4