Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 395 of 982
REJ09B0023-0400
BSC Register Setting CPU Access DMAC Access
CSnBCR
Idle
Setting
CS3WCR.
WTRP
Setting
CS3WCR.
TRWL
Setting
Read to
Read
Write to
Write
Read to
Write
Write to
Read
Read to
Write
Write to
Read
4 2 0 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 2 1 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 2 2 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 2 3 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5 5
4 3 0 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 3 1 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 3 2 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5 5
4 3 3 5/5/5/5 6/6/6/6 5/5/5/5 6/6/6/6 5 6
n (n>=6) All n+1 n/n/n/n All n+1 n/n/n/n n+1 n
Notes: The minimum number of idle cycles in CPU Access is described sequentially for Iφ:Bφ
(4:1/3:1/2:1/1:1).
1. DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
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