Renesas HD6417641 - Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 393 of 982
REJ09B0023-0400
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC
Dual Address Mode for the SDRAM Interface
BSC Register Setting CPU Access DMAC Access
CSnBCR
Idle
Setting
CS3WCR.
WTRP
Setting
CS3WCR.
TRWL
Setting
Read to
Read
Write to
Write
Read to
Write
Write to
Read
Read to
Write
Write to
Read
0 0 0 1/1/1/2 1/1/2/3 3/3/4/5 0/0/0/0 2 0
0 0 1 1/1/1/2 1/1/2/3 3/3/4/5 1/1/1/1 2 1
0 0 2 1/1/1/2 2/2/2/3 3/3/4/5 2/2/2/2 2 2
0 0 3 1/1/1/2 3/3/3/3 3/3/4/5 3/3/3/3 2 3
0 1 0 2/2/2/2 1/1/2/3 3/3/4/5 1/1/1/1 2 1
0 1 1 2/2/2/2 2/2/2/3 3/3/4/5 2/2/2/2 2 2
0 1 2 2/2/2/2 3/3/3/3 3/3/4/5 3/3/3/3 2 3
0 1 3 2/2/2/2 4/4/4/4 3/3/4/5 4/4/4/4 2 4
0 2 0 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
0 2 1 3/3/3/3 3/3/3/3 3/3/4/5 3/3/3/3 3 3
0 2 2 3/3/3/3 4/4/4/4 3/3/4/5 4/4/4/4 3 4
0 2 3 3/3/3/3 5/5/5/5 3/3/4/5 5/5/5/5 3 5
0 3 0 4/4/4/4 3/3/3/3 4/4/4/5 3/3/3/3 4 3
0 3 1 4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4 4 4
0 3 2 4/4/4/4 5/5/5/5 4/4/4/5 5/5/5/5 4 5
0 3 3 4/4/4/4 6/6/6/6 4/4/4/5 6/6/6/6 4 6
1 0 0 2/2/2/2 1/1/2/3 3/3/4/5 1/1/1/1 2 1
1 0 1 2/2/2/2 1/1/2/3 3/3/4/5 1/1/1/1 2 1
1 0 2 2/2/2/2 2/2/2/3 3/3/4/5 2/2/2/2 2 2
1 0 3 2/2/2/2 3/3/3/3 3/3/4/5 3/3/3/3 2 3
1 1 0 2/2/2/2 1/1/2/3 3/3/4/5 1/1/1/1 2 1
1 1 1 2/2/2/2 2/2/2/3 3/3/4/5 2/2/2/2 2 2
1 1 2 2/2/2/2 3/3/3/3 3/3/4/5 3/3/3/3 2 3
1 1 3 2/2/2/2 4/4/4/4 3/3/4/5 4/4/4/4 2 4
1 2 0 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
1 2 1 3/3/3/3 3/3/3/3 3/3/4/5 3/3/3/3 3 3
1 2 2 3/3/3/3 4/4/4/4 3/3/4/5 4/4/4/4 3 4