Renesas HD6417641 - Port G; Register Description; Figure 23.7 Port G

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 856 of 982
REJ09B0023-0400
23.7 Port G
Port G comprises a 6-bit input/output port and an 8-bit input port with the pin configuration shown
in figure 23.7. Each pin is controlled by the port G control register (PGCR) in the PFC.
Port G
PTG13 (input/output)
PTG12 (input/output)
PTG11 (input/output)
PTG10 (input/output)/SDA (input/output)
PTG9 (input/output)/SCL (input/output)
PTG8 (input/output)
PTG7 (input)/AN7 (input)
PTG6 (input)/AN6 (input)
PTG5 (input)/AN5 (input)
PTG4 (input)/AN4 (input)
PTG3 (input)/AN3 (input)
PTG2 (input)/AN2 (input)
PTG1 (input)/AN1 (input)
PTG0 (input)/AN0 (input)
Figure 23.7 Port G
23.7.1 Register Description
Port G registers has the following register.
• Port G data register (PGDR)