Renesas HD6417641 - Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 603 of 982
REJ09B0023-0400
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TGR_4
TDDR
TCNT_3
TCNT_4
Initial output
Time
Active level
TCNT_3, 4 count start
(TSTR setting)
Complementary
PWM mode
(TMDR setting)
Positive phase
output
Negative phase
output
Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)