Renesas HD6417641 - Figure 3.21 Modulo Addressing

Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 136 of 982
REJ09B0023-0400
MS and ME are set to specify the start and end addresses, and then later to set the DMX or DMY
bit to 1.
When the X/Y data transfer instruction set in DMX/DMY is executed, the address register
contents before update are compared with ME*
1
. If they match, modulo start address MS is stored
in the address register as the updated value*
2
. If non-update address register addressing is
specified for the X/Y data transfer instruction, the address pointer will not return to modulo start
address MS even though the address register contents match ME.
Notes: 1. Bits 1 to 15 of the address register are used for comparison. Though ME retains its
previous value for bit 0, 0 must always be written to bit 0.
2. The MS value is stored in bits 1 to 15 of the address register. Though MS retains its
previous value for bit 0, 0 must always be written to bit 0.
The maximum modulo size is 64-kbytes. This is sufficient for accessing the X or Y data memory.
Figure 3.21 shows a block diagram of modulo addressing.
ALU
R8 [Ix]
31
31 1615
DMX DMY
Instr (MOVX/Y)
15
15 1
1
0
0
R9 [Iy]
31 0
R4 [Ax]
R5 [Ax]
ABx
15 1
15 1
ME
31 1615
15 1
0
+2
+0
+2
+0
AU
ABx
XAB
YAB
MS
CMP
CONT
R6 [Ay]
R7 [Ay]
Figure 3.21 Modulo Addressing