Renesas HD6417641 - SDRAM Control Register (SDCR)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 314 of 982
REJ09B0023-0400
12.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual
reset and in the standby mode.
Bit Bit Name
Initial
Value R/W Description
31 to 21  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20
19
A2ROW1
A2ROW0
0
0
R/W
R/W
Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (Setting prohibited)
18  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
17
16
A2COL1
A2COL0
0
0
R/W
R/W
Number of Bits of Column Address for Area 2
Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (Setting prohibited)
15, 14  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.