Renesas HD6417641 - Timer Output Control Register (TOCR); Table 18.26 Output Level Select Function

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 557 of 982
REJ09B0023-0400
18.3.11 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle
output in complementary PWM mode/reset synchronized PWM mode, and controls output level
inversion of PWM output.
Bit Bit Name
Initial
value R/W Description
7  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
6 PSYE 0 R/W PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output
synchronized with the PWM period.
0: Toggle output is disabled
1: Toggle output is enabled
5 to 2  All 0 R Reserved
These bits are always read as 0. Only 0 should be
written to this bit.
1 OLSN 0 R/W Output Level Select N
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 18.26
0 OLSP 0 R/W Output Level Select P
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 18.27.
Table 18.26 Output Level Select Function
Bit 1 Function
Compare Match Output
OLSN Initial Output Active Level
Increment Count Decrement Count
0 High level Low level High level Low level
1 Low level High level Low level High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.