Renesas HD6417641 - Register Descriptions; Standby Control Register (STBCR)

Section 6 Power-Down Modes
Rev. 4.00 Sep. 14, 2005 Page 166 of 982
REJ09B0023-0400
6.2 Register Descriptions
The following registers are used in the low power-consumption modes. For the addresses and
access sizes of these registers, see section 24, List of Registers.
• Standby control register (STBCR)
• Standby control register 2 (STBCR2)
• Standby control register 3 (STBCR3)
• Standby control register 4 (STBCR4)
6.2.1 Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the state
of the power-down mode. This register is initialized (to H'00) by a power-on reset but retains its
previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit Bit Name
Initial
Value R/W Description
7 STBY 0 R/W Software Standby
Specifies transition to software standby mode.
0: Executing SLEEP instruction puts chip into sleep
mode.
1: Executing SLEEP instruction puts chip into
software standby mode.
6 to 0  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.