Renesas HD6417641 - USBEP1 Receive Data Size Register (USBEPSZ1); USB Trigger Register (USBTRG)

Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 759 of 982
REJ09B0023-0400
20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)
USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The
endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this
register refers to the currently selected FIFO (that can be read by CPU).
USBEPSZ1 can be initialized to H'00 by a power-on reset.
Bit Bit Name
Initial
Value R/W Description
7 to 0  All 0 R Number of bytes received by endpoint 1
20.3.17 USB Trigger Register (USBTRG)
USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint.
USBTRG can be initialized to H'00 by a power-on reset.
Bit Bit Name
Initial
Value R/W Description
7  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
6 EP3PKTE 0 W EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
5 EP1RDFN 0 W EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-FIFO configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
4 EP2PKTE 0 W EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 FIFO buffer, the transmit data is fixed by
writing 1 to this bit.
3  0 R Reserved
The write value should always be 0.