Renesas HD6417641 - Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles)

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 953 of 982
REJ09B0023-0400
Trc Trc Tr cTrrTpw
Tp
(Hi-Z)*
3
t
AD3
t
AD3
t
CSD2
t
CSD2
t
CSD2
t
CSD2
t
CASD2
t
DQMD2
t
CASD2
t
CASD2
t
RASD2
t
CKED2
t
CKED2
t
RASD2
t
RASD2
t
RWD2
t
RWD2
t
RASD2
t
AD3
t
AD3
CKIO
A25 to A0
CSn
RD/WR
A12/A11*
1
D31 to D0
RASU/L
CASU/L
BS
CKE
DQMxx
DACKn,
TENDn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn and TENDn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)