Renesas HD6417641 - USBFIFO Clear Register (USBFCLR)

Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 761 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
4 EP2DE 0 R EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data
3 to 1  All 0 R Reserved
The write value should always be 0.
0 EP0iDE 0 R EP0i Data Present
This bit is set when the endpoint 0 transmit FIFO
buffer contains valid data.
20.3.19 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
USBFCLR can be initialized to H'00 by a power-on reset.
Bit Bit Name
Initial
Value R/W Description
7  0  Reserved
The write value should always be 0.
6 EP3CLR 0 W EP3 Clear
When 1 is written to this bit, the endpoint 3 transmit
FIFO buffer is initialized.
5 EP1CLR 0 W EP1 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 1 receive FIFO buffer are initialized.
4 EP2CLR 0 W EP2 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 2 transmit FIFO buffer are initialized.
3, 2  All 0  Reserved
The write value should always be 0.
1 EP0oCLR 0 W EP0o Clear
When 1 is written to this bit, the endpoint 0 receive
FIFO buffer is initialized.