Renesas HD6417641 - Clock Timing; Table 25.6 Clock Timing

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 916 of 982
REJ09B0023-0400
25.3.1 Clock Timing
Table 25.6 Clock Timing
Conditions: V
CC
Q = 3.0 V to 3.6 V, V
CC
= 1.8 V ± 5%, AV
CC
= 3.0 V to 3.6 V, V
SS
Q = V
SS
= AV
SS
= 0 V, Ta = −40°C to +85°C
Item Symbol Min. Max. Unit Figure(s)
EXTAL clock input frequency f
EX
10 25 MHz
EXTAL clock input cycle time t
EXcyc
40 100 ns
EXTAL clock input pulse low width t
EXL
7  ns
EXTAL clock input pulse high width t
EXH
7  ns
EXTAL clock input rising time t
EXR
 4 ns
EXTAL clock falling time t
EXF
 4 ns
25.2
CKIO clock input frequency f
CK
20 50 MHz
CKIO clock input cycle time t
CKcyc
20 50 ns
CKIO clock input low pulse width t
CKIL
7  ns
CKIO clock input high pulse width t
CKIH
7  ns
CKIO clock input rising time t
CKIr
 3 ns
CKIO clock input falling time t
CKIf
 3 ns
25.3
CKIO, CKIO2 clock output frequency f
OP
20 50 MHz
CKIO, CKIO2 clock output cycle time t
cyc
20 50 ns
CKIO, CKIO2 clock output pulse low width t
CKOL
7  ns
CKIO, CKIO2 clock output pulse high width t
CKOH
7  ns
CKIO, CKIO2 clock output rising time t
CKOR
 5 ns
CKIO, CKIO2 clock falling time t
CKOF
 5 ns
25.4
Oscillation settling time
(after power-on reset)
t
OSC1
10  ms 25.5
Phase difference between CKIO and
CKIO2
t
phckio2
 3 ns 25.6
Oscillation settling time 1
(after standby mode)
t
OSC2
10  ms 25.7
Oscillation settling time 2
(after standby mode)
t
OSC3
10  ms 25.8