Renesas HD6417641 - Page 18

Rev. 4.00 Sep. 14, 2005 Page xviii of l
12.4.4 SDRAM Control Register (SDCR)....................................................................... 314
12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 317
12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 319
12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 319
12.4.8 Reset Wait Counter (RWTCNT) .......................................................................... 320
12.5 Operating Description........................................................................................................ 321
12.5.1 Endian/Access Size and Data Alignment.............................................................. 321
12.5.2 Normal Space Interface ........................................................................................ 324
12.5.3 Access Wait Control............................................................................................. 329
12.5.4 CSn Assert Period Expansion............................................................................... 331
12.5.5 MPX-I/O Interface................................................................................................ 332
12.5.6 SDRAM Interface................................................................................................. 335
12.5.7 Burst ROM (Clock Asynchronous) Interface ....................................................... 376
12.5.8 Byte-Selection SRAM Interface ........................................................................... 377
12.5.9 Burst MPX-I/O Interface...................................................................................... 382
12.5.10 Burst ROM Interface (Clock Synchronous).......................................................... 386
12.5.11 Wait between Access Cycles................................................................................ 387
12.5.12 Bus Arbitration ..................................................................................................... 399
12.5.13 Others.................................................................................................................... 401
Section 13 Direct Memory Access Controller (DMAC)...................................405
13.1 Features.............................................................................................................................. 405
13.2 Input/Output Pins...............................................................................................................407
13.3 Register Descriptions......................................................................................................... 408
13.3.1 DMA Source Address Registers (SAR)................................................................ 409
13.3.2 DMA Destination Address Registers (DAR)........................................................ 409
13.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 409
13.3.4 DMA Channel Control Registers (CHCR) ........................................................... 410
13.3.5 DMA Operation Register (DMAOR) ................................................................... 416
13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1).................... 421
13.4 Operation ........................................................................................................................... 424
13.4.1 DMA Transfer Flow ............................................................................................. 424
13.4.2 DMA Transfer Requests....................................................................................... 426
13.4.3 Channel Priority.................................................................................................... 429
13.4.4 DMA Transfer Types............................................................................................ 432
13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 440
13.4.6 Completion of DMA Transfer .............................................................................. 444
13.4.7 Notes on Usage..................................................................................................... 445
13.4.8 Notes On DREQ Sampling When DACK is Divided in External Access............ 446