Renesas HD6417641 - Page 200

Section 4 Clock Pulse Generator (CPG)
Rev. 4.00 Sep. 14, 2005 Page 150 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
11, 10  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9
8
STC1
STC0
0
0
R/W
R/W
Frequency multiplication ratio of PLL circuit 1
00: × 1 time
01: × 2 times
10: × 3 times
11: × 4 times
7, 6  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
5
4
IFC1
IFC0
0
0
R/W
R/W
Internal Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
3, 2  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1
0
PFC1
PFC0
1
1
R/W
R/W
Peripheral Clock Frequency Division Ratio
These bits specify the division ratio of the peripheral
clock frequency with respect to the output frequency
of PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time