Renesas HD6417641 - Page 234

Section 7 Cache
Rev. 4.00 Sep. 14, 2005 Page 184 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W Description
31 to 17  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
16 LE 0 R/W Lock Enable
This bit enables or disables the cache locking function.
0: Cache locking mode is entered when SR.DSP=1
1: Cache locking mode is entered regardless of the
value of SR.DSP
15 to 10  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9
8
W3LOAD
W3LOCK
0
0
R/W
R/W
Way 3 Load
Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.
7 to 2  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1
0
W2LOAD
W2LOCK
0
0
R/W
R/W
Way 2 Load
Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.