Renesas HD6417641 - Page 26

Rev. 4.00 Sep. 14, 2005 Page xxvi of l
23.4.2 Port D Data Register (PDDR)............................................................................... 850
23.5 Port E................................................................................................................................. 851
23.5.1 Register Description ............................................................................................. 852
23.5.2 Port E Data Register (PEDR)................................................................................ 852
23.6 Port F ................................................................................................................................. 853
23.6.1 Register Description ............................................................................................. 854
23.6.2 Port F Data Register (PFDR)................................................................................ 854
23.7 Port G................................................................................................................................. 856
23.7.1 Register Description ............................................................................................. 856
23.7.2 Port G Data Register (PGDR)............................................................................... 857
23.7.3 Port G Internal Block Diagram............................................................................. 859
23.8 Port H................................................................................................................................. 860
23.8.1 Register Description ............................................................................................. 860
23.8.2 Port H Data Register (PHDR)............................................................................... 861
23.9 Port J.................................................................................................................................. 862
23.9.1 Register Description ............................................................................................. 862
23.9.2 Port J Data Register (PJDR) ................................................................................. 863
Section 24 List of Registers...............................................................................865
24.1 Register Addresses
(by functional module, in order of the corresponding section numbers) ........................... 866
24.2 Register Bits....................................................................................................................... 876
24.3 Register States in Each Operating Mode ........................................................................... 896
Section 25 Electrical Characteristics.................................................................907
25.1 Absolute Maximum Ratings .............................................................................................. 907
25.1.1 Power-On Sequence.............................................................................................. 908
25.2 DC Characteristics............................................................................................................. 910
25.3 AC Characteristics............................................................................................................. 915
25.3.1 Clock Timing........................................................................................................ 916
25.3.2 Control Signal Timing.......................................................................................... 920
25.3.3 AC Bus Timing..................................................................................................... 923
25.3.4 Basic Timing......................................................................................................... 925
25.3.5 Bus Cycle of Byte-Selection SRAM..................................................................... 932
25.3.6 Burst ROM Read Cycle........................................................................................ 934
25.3.7 Synchronous DRAM Timing................................................................................ 935
25.3.8 Peripheral Module Signal Timing......................................................................... 954
25.3.9 Multi Function Timer Pulse Unit Timing............................................................. 956
25.3.10 POE Module Signal Timing ................................................................................. 957
25.3.11 I
2
C Module Signal Timing.................................................................................... 958