Renesas HD6417641 - Page 295

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 245 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
5
4
IDA1
IDA0
0
0
R/W
R/W
Instruction Fetch/Data Access Select A
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
data access cycle
3
2
RWA1
RWA0
0
0
R/W
R/W
Read/Write Select A
Select the read cycle or write cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
1
0
SZA1
SZA0
0
0
R/W
R/W
Operand Size Select A
Select the operand size of the bus cycle for the
channel A break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access