Renesas HD6417641 - Page 332

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 282 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
27
26
25
IWRWD2
IWRWD1
IWRWD0
1
1
1
R/W
R/W
R/W
Idle Cycles for Another Space Read-Write
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target access cycle is a read-write one in
which continuous accesses switch between different
spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
24
23
22
IWRWS2
IWRWS1
IWRWS0
1
1
1
R/W
R/W
R/W
Idle Cycles for Read-Write in the Same Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-write cycle of which
continuous accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted