Renesas HD6417641 - Page 340

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 290 of 982
REJ09B0023-0400
• CS4WCR
Bit Bit Name
Initial
Value R/W Description
31 to 21  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read access cycle
and asserts the RD/WR signal at the write timing.
19  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
18
17
16
WW2
WW1
WW0
0
0
0
R/W
R/W
R/W
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.