Renesas HD6417641 - Page 349

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 299 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
1
0
HW1
HW0
0
0
R/W
R/W
Delay Cycles from RD, WEn Negation to Address,
CSn Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6BWCR
Bit Bit Name
Initial
Value R/W Description
31 to 21  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
19 to 13  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12
11
SW1
SW0
0
0
R/W
R/W
Number of Delay Cycles from Address, CSn Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address, CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles