Renesas HD6417641 - Page 359

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 309 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
2  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
1
0
WTRC1*
WTRC0
0
0
R/W
R/W
Number of Idle Cycles from REF Command/Self-
Refresh Release to ACTV/REF/MRS Command
Specify the number of minimum idle cycles during the
periods shown below.
• From issuing of the REF command to issuing of the
ACTV/REF/MRS command
• From releasing self-refresh to issuing of the
ACTV/REF/MRS command
The setting for areas 2 and 3 is common.
00: 2 cycles (Initial value)
01: 3 cycles
10: 5 cycles
11: 8 cycles
Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0],
and WTRC[1:0] bit settings are common. If only one area is connected to the SDRAM,
specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM.
Burst MPX-IO:
• CS6BWCR
Bit Bit Name
Initial
Value R/W Description
31 to 22  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
21
20
MPXAW1
MPXAW0
0
0
R/W
R/W
Number of Address Cycle Waits
Specify the number of waits to be inserted in the
address cycle.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles