Renesas HD6417641 - Page 581

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 531 of 982
REJ09B0023-0400
• TIORL_0, TIORL_3, TIORL_4
Bit Bit Name
Initial
value R/W Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D3 to D0
Specify the function of TGRD.
When TGRD is used as the buffer register of TGRB,
this setting is disabled, and input capture/output
compare does not occur.
See the following tables.
TIORL_0: Table 18.11
TIORL_3: Table 18.15
TIORL_4: Table 18.17
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C3 to C0
Specify the function of TGRC.
When TGRC is used as the buffer register of TGRA,
this setting is disabled, and input capture/output
compare does not occur.
See the following tables.
TIORL_0: Table 18.19
TIORL_3: Table 18.23
TIORL_4: Table 18.25