Segger J-Link - Availability and Limitations of Monitor Mode

To Next Page

To Previous Page

275

8.3 Availability and limitations of monitor mode

Many CPUs only support one of these debug modes, halt mode or monitor mode. In

the following it is explained for which CPU cores monitor mode is available and any

limitations, if any.

8.3.1 Cortex-M3

See Cortex-M4 on page 275.

8.3.2 Cortex-M4

For Cortex-M4, monitor mode debugging is supported. The monitor code provided by

SEGGER can easily be linked into the user application.

Considerations & Limitations

• The user-specific monitor functions must not block the generic monitor for more

than 100ms.

• Manipulation of the stackpointer register (SP) from within the IDE is not possible

as the stackpointer is necessary for resuming the user application on Go().

• The unlimited number of flash breakpoints feature cannot be used in monitor

mode. This restriction may be removed in a future version.

• It is not possible to debug the monitor itself, when using monitor mode.

Other manuals for Segger J-Link