Segger J-Link - At91 Sam9

J-Link / J-Trace (UM08001) © 2004-2017 SEGGER Microcontroller GmbH & Co. KG
389
RDI Sample
SetJTAGSpeed(30); // Set JTAG speed to 30 kHz
Reset(0, 0);
Write32(0xFFFFFD00, 0xA5000004); // Perform peripheral reset
Write32(0xFFFFFD44, 0x00008000); // Disable watchdog
Write32(0xFFFFFC20, 0x00000601); // Set PLL
Delay(200);
Write32(0xFFFFFC2C, 0x00191C05); // Set PLL and divider
Delay(200);
Write32(0xFFFFFC30, 0x00000007); // Select master clock and processor clock
Write32(0xFFFFFF60, 0x00320300); // Set flash wait states
SetJTAGSpeed(12000);
15.2.2 AT91SAM9
15.2.2.1 JTAG settings
We recommend using adaptive clocking.
This information is applicable to the following devices:
• AT91RM9200
• AT91SAM9260
• AT91SAM9261
• AT91SAM9262
• AT91SAM9263