376 CHAPTER 14 Trace
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
14.2 Tracing via trace pins
This is the most common tracing method, as it also allows to use streaming trace.
The target outputs trace data + a trace clock on specific pins. These pins are sampled
by J-Trace and trace data is collected. As trace data is output with a relatively high
frequency (easily >= 100 MHz on modern embedded systems) a high end hardware
is necessary on the trace probe (J-Trace) to be able to sample and digest the trace
data sent by the target CPU. Our J-Trace models support up to 4-bit trace which can
be manually set by the user by overwriting the global variable
JLINK_TRACE_Portwidth which is set to 4 by default. Please refer to Global DLL vari-
ables
on page 213.
14.2.1 Cortex-M specifics
The trace clock output by the CPU is usually 1/2 of the speed of the CPU clock, but
trace data is output double data rate, meaning on each edge of the trace clock. There
are usually 4 trace data pins on which data is output, resulting in 1 byte trace data
being output per trace clock (2 * 4 bits).
14.2.2 Trace signal timing
There are certain signal timings that must be met, such as rise/fall timings for clock
and data, as well as setup and hold timings for the trace data. These timings are
specified by the vendor that designs the trace hardware unit (e.g. ARM that provides
the ETM as a trace component for their cores). For more information about what tim-
ings need to be met for a specific J-Trace model, please refer to
J-Link / J-Trace mod-
els
on page 30.
14.2.3 Adjusting trace signal timing on J-Trace
Some target CPUs do not meet the trace timing requirements when it comes to the
trace data setup times (some output the trace data at the same time they output a
trace clock edge, resulting on effectively no setup time). Another case where timing
requirements may not be met is for example when having one trace data line on a
hardware that is longer than the other ones (necessary due to routing requirements
on the PCB). For such cases, higher end J-Trace models, like J-Trace PRO, allow to
adjust the timing of the trace signals, inside the J-Trace firmware. For example, in
case the target CPU does not provide a (sufficient) trace data setup time, the data
sample timing can be adjusted inside J-Trace. This causes the data edges to be rec-
ognized by J-Trace delayed, virtually creating a setup time for the trace data.
The trace signals can be adjusted via the
TraceSampleAdjust command string. For
more information about the syntax this command string, please refer to
Command
strings
on page 223. For more information about how to use command strings in dif-
ferent environments, please refer to
Using command strings on page 241.
The following graphic illustrates how a adjustment of the trace data signal affects the
sampling of the trace data inside the J-Trace firmware.
• TCLK = trace clock output by target
• TDx = Trace data 0-3 output by target
•TDx +
Δt
d
= Trace data seen by J-Trace firmware
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