436 CHAPTER 17 Background information
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2004-2017 SEGGER Microcontroller GmbH & Co. KG
17.1 JTAG
JTAG is the acronym for Joint Test Action Group. In the scope of this document,
"the JTAG standard" means compliance with IEEE Standard 1149.1-2001.
17.1.1 Test access port (TAP)
JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can
provide access to many test support functions built into a component. It is composed
as a minimum of the three input connections (TDI, TCK, TMS) and one output con-
nection (TDO). An optional fourth input connection (nTRST) provides for asynchro-
nous initialization of the test logic.
17.1.2 Data registers
JTAG requires at least two data registers to be present: the bypass and the bound-
ary-scan register. Other registers are allowed but are not obligatory.
Bypass data register
A single-bit register that passes information from TDI to TDO.
Boundary-scan data register
A test data register which allows the testing of board interconnections, access to
input and output of components when testing their system logic and so on.
17.1.3 Instruction register
The instruction register holds the current instruction and its content is used by the
TAP controller to decide which test to perform or which data register to access. It
consist of at least two shift-register cells.
PIN Type Explanation
TCK Input
The test clock input (TCK) provides the clock for the test
logic.
TDI Input
Serial test instructions and data are received by the test
logic at test data input (TDI).
TMS Input
The signal received at test mode select (TMS) is
decoded by the TAP controller to control test operations.
TDO Output
Test data output (TDO) is the serial output for test
instructions and data from the test logic.
nTRST
Input
(optional)
The optional test reset (nTRST) input provides for asyn-
chronous initialization of the TAP controller.
Table 17.1: Test access port
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