Segger J-Link - Pin J-Link Connector

418 CHAPTER 16 Target interfaces and adapters
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
16.1 20-pin J-Link connector
16.1.1 Pinout for JTAG
J-Link and J-Trace have a JTAG connector compati-
ble to ARM’s Multi-ICE. The JTAG connector is a 20
way Insulation Displacement Connector (IDC) keyed
box header (2.54mm male) that mates with IDC
sockets mounted on a ribbon cable.
*On later J-Link products like the J-link ULTRA,
these pins are reserved for firmware extension pur-
poses. They can be left open or connected to GND in
normal debug environment. They are not essential
for JTAG/SWD in general.
The following table lists the J-Link / J-Trace JTAG pinout.
PIN SIGNAL TYPE Description
1VTref Input
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
2
Not con-
nected
NC This pin is not connected in J-Link.
3nTRST Output
JTAG Reset. Output from J-Link to the Reset signal of the
target JTAG port. Typically connected to nTRST of the target
CPU. This pin is normally pulled HIGH on the target to avoid
unintentional resets when there is no connection.
5TDI Output
JTAG data input of target CPU. It is recommended that this
pin is pulled to a defined state on the target board. Typically
connected to TDI of the target CPU.
7TMS Output
JTAG mode set input of target CPU. This pin should be
pulled up on the target. Typically connected to TMS of the
target CPU.
9TCK Output
JTAG clock signal to target CPU. It is recommended that this
pin is pulled to a defined state of the target board. Typically
connected to TCK of the target CPU.
11 RTCK Input
Return test clock signal from the target. Some targets must
synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, you can use a returned, and
retimed, TCK to dynamically control the TCK rate. J-Link
supports adaptive clocking, which waits for TCK changes to
be echoed correctly before making further changes. Con-
nect to RTCK if available, otherwise to GND.
13 TDO Input
JTAG data output from target CPU. Typically connected to
TDO of the target CPU.
Table 16.1: J-Link / J-Trace pinout
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
VTref
nTRST
TDI
TMS
TCK
RTCK
TDO
RESET
DBGRQ
5V-Supply
NC
GND
GND
GND
GND
GND*
GND*
GND*
GND*
GND