456 CHAPTER 19 Semihosting
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
19.3 Implementation
In general, there are two ways of implement semihosting which are explained in the
following:
• SVC instruction (called SWI on legacy CPUs)
• Breakpoint instruction
• J-Link GDBServer optimized version
19.3.1 SVC instruction
Inside printf() calls etc. that shall perform semihosting, an SVC instruction is present
which causes the CPU to issue a software interrupt and jump to the SVC exception
handler. The debugger usually sets a breakpoint on the first instruction of the SVC
exception handler or sets a vector catch that has the same effect but does not waste
one hardware breakpoint. If vector catch is available depends on the CPU. Once the
CPU has been halted, the debugger can identify the cause of the SVC exception by
analyzing the SVC instruction that caused the exception. In the instruction there is a
SVC reason/number encoded. The number may differ if the CPU was in ARM or
Thumb mode when the SVC instruction was executed. The following SVC reasons are
revsered for semihosting:
• ARM mode: 0x123456
• Thumb mode: 0xAB
Once the debugger has performed the semihosting operation and evaluated the com-
mand, it will restart the target CPU right behind the SVC instruction that caused the
semihosting call. So it is debuggers responsibility to perform the exception return.
Disadvantages
If the SVC instruction is also used by the user application or a operating system on
the target, the CPU will be halted on every semihosting exception and be restarted
by the debugger. This affects real-time behavior of the target application.
19.3.2 Breakpoint instruction
A breakpoint instruction is compiled into the code that makes use of semihosting
(usually somewhere inside the printf() function in a library). The CPU halts as soon
as the breakpoint instruction is hit and allows the debugger to perform semihosting
operations. Once the CPU has been halted, the debugger is able to determine the halt
reason by analyzing the breakpoint instruction that caused the halt. In the break-
point instruction, a "halt reason" can be encoded. The halt reason may differ if the
breakpoint instruction is an ARM instruction or Thumb instruction. The following halt
reasons are reserved for semihosting:
• ARM mode: 0x123456
• Thumb mode: 0xAB
Disadvantages
Having a breakpoint instruction compiled in a library call will make it necessary to
have different compile options for debug and release configurations as the target
application will not run stand-alone, without debugger intervention.
19.3.3 J-Link GDBServer optimized version
When using J-Link GDBServer with a GDB-based environment, there is a third imple-
mentation for semihosting available which is a hybrid of the other implementations,
combining the advantages of both. With this implementation, an SVC instruction with
the usual SVC reason is used to issue a semihosting call but the debugger does not
set a breakpoint or vector catch on the start of the SVC exception handler. Instead,
the SVC exception handler provides some code that detects if the reason was a semi-
hosting call, if yes it immediately performs a return from exception on which the
debugger has set a hardware breakpoint. This allows the application to continue nor-
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