Segger J-Link - Assignment of Trace Information Pins between ETM Architecture Versions

428 CHAPTER 16 Target interfaces and adapters
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
16.2.3 Assignment of trace information pins between ETM
architecture versions
The following table show different names for the trace signals depending on the ETM
architecture version.
16.2.4 Trace signals
Data transfer is synchronized by TRACECLK.
16.2.4.1 Signal levels
The maximum capacitance presented by J-Trace at the trace port connector, including
the connector and interfacing logic, is less than 6pF. The trace port lines have a
matched impedance of 50.
The J-Trace unit will operate with a target board that has a supply voltage range of
3.0V-3.6V.
16.2.4.2 Clock frequency
For capturing trace port signals synchronous to TRACECLK, J-Trace supports a
TRACECLK frequency of up to 200MHz. The following table shows the TRACECLK fre-
quencies and the setup and hold timing of the trace signals with respect to TRACE-
CLK.
Trace signal ETMv1 ETMv2 ETMv3
Trace signal 1 PIPESTAT[0] PIPESTAT[0] TRACEDATA[0]
Trace signal 2 PIPESTAT[1] PIPESTAT[1] TRACECTL
Trace signal 3 PIPESTAT[2] PIPESTAT[2] Logic 1
Trace signal 4 TRACESYNC PIPESTAT[3] Logic 0
Trace signal 5 TRACEPKT[0] TRACEPKT[0] Logic 0
Trace signal 6 TRACEPKT[1] TRACEPKT[1] TRACEDATA[1]
Trace signal 7 TRACEPKT[2] TRACEPKT[2] TRACEDATA[2]
Trace signal 8 TRACEPKT[3] TRACEPKT[3] TRACEDATA[3]
Trace signal 9 TRACEPKT[4] TRACEPKT[4] TRACEDATA[4]
Trace signal 10 TRACEPKT[5] TRACEPKT[5] TRACEDATA[5]
Trace signal 11 TRACEPKT[6] TRACEPKT[6] TRACEDATA[6]
Trace signal 12 TRACEPKT[7] TRACEPKT[7] TRACEDATA[7]
Trace signal 13 TRACEPKT[8] TRACEPKT[8] TRACEDATA[8]
Trace signal 14 TRACEPKT[9] TRACEPKT[9] TRACEDATA[9]
Trace signal 15 TRACEPKT[10] TRACEPKT[10] TRACEDATA[10]
Trace signal 16 TRACEPKT[11] TRACEPKT[11] TRACEDATA[11]
Trace signal 17 TRACEPKT[12] TRACEPKT[12] TRACEDATA[12]
Trace signal 18 TRACEPKT[13] TRACEPKT[13] TRACEDATA[13]
Trace signal 19 TRACEPKT[14] TRACEPKT[14] TRACEDATA[14]
Trace signal 20 TRACEPKT[15] TRACEPKT[15] TRACEDATA[15]
Table 16.8: Assignment of trace information pins between ETM architecture versions
Parameter Min. Max. Explanation
Tperiod 5ns 1000ns Clock period
Fmax 1MHz 200MHz Maximum trace frequency
Tch 2.5n s - H igh pulse width
Tcl 2.5ns - Low pulse width
Tsh 2.5ns - Data setup high
Table 16.9: Clock frequency