Segger J-Link - Pinout for SPI

424 CHAPTER 16 Target interfaces and adapters
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
16.1.4 Pinout for SPI
*On later J-Link products like the J-link ULTRA,
these pins are reserved for firmware extension pur-
poses. They can be left open or connected to GND
in normal debug environment.
The following table lists the pinout for the SPI inter-
face on J-Link.
Pins 4, 6, 8, 10, 12 are GND pins connected to GND in J-Link. They should also be
connected to GND in the target system.
PIN SIGNAL TYPE Description
1VTref Input
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
2
Not con-
nected
NC Leave open on target side
3
Not con-
nected
NC Leave open on target side
5DI Output
Data-input of target SPI. Output of J-Link, used to transmit
data to the target SPI.
7 nCS Output Chip-select of target SPI (active LOW).
9 CLK Output SPI clock signal.
11
Not con-
nected
NC Leave open on target side
13 DO Input
Data-out of target SPI. Input of J-Link, used to receive data
from the target SPI.
15 nRESET I/O
Target CPU reset signal. Typically connected to the RESET
pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET". This signal is an active low signal.
17
Not con-
nected
NC Leave open on target side
19
5V-Sup-
ply
Output
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
pin. For more information about how to enable/disable the
power supply, please refer to
Target power supply on
page 420.
Table 16.6: J-Link / J-Trace pinout
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
VTref
NC
DI
nCS
CLK
NC
DO
nRESET
NC
5V-Supply
NC
GND
GND
GND
GND
GND*
GND*
GND*
GND*
GND