Segger J-Link - Page 419

J-Link / J-Trace (UM08001) © 2004-2017 SEGGER Microcontroller GmbH & Co. KG
419
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They
should also be connected to GND in the target system.
16.1.1.1 Target board design
We strongly advise following the recommendations given by the chip manufacturer.
These recommendations are normally in line with the recommendations given in the
table
Pinout for JTAG on page 418. In case of doubt you should follow the recommen-
dations given by the semiconductor manufacturer.
You may take any female header following the specifications of DIN 41651.
For example:
15 nRESET I/O
Target CPU reset signal. Typically connected to the RESET
pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET". This signal is an active low signal.
17 DBGRQ NC
This pin is not connected in J-Link. It is reserved for com-
patibility with other equipment to be used as a debug
request signal to the target system. Typically connected to
DBGRQ if available, otherwise left open.
19
5V-Sup-
ply
Output
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
pin. For more information about how to enable/disable the
power supply, please refer to
Target power supply on
page 420.
Harting part-no. 09185206803
Molex part-no. 90635-1202
Tyco Electronics part-no. 2-215882-0
PIN SIGNAL TYPE Description
Table 16.1: J-Link / J-Trace pinout